Two-step Wet Etching Process Research Articles

A two-step wet etching process of PZT thin film with ultra-low undercut for MEMS applications

Wet etching methods of lead zirconate titanate (PZT) film suffer from high residual risk and severe undercut erosion. In this study, a two-step etching approach replace with the traditional concept of multi-acid mixing etchant, which increases the precision of PZT film and fixes the residual issues that were difficult to avoid in the conventional scheme. The two-step etching of the PZT film's mechanism is investigated using XRD and TEM. The impact of the etchant's composition ratio on the etching effect is demonstrated, and the ideal process range and debugging direction can be accurately identified. The undercut ratio (0.62) of the etching method proposed in this study is substantially lower than that in prior studies. In addition, the etching rate and selectivity between photoresists are 60 nm/s and 1.14, respectively. The sidewall forms an inclined plane of around 30 degrees due to the crystal orientation dependent etch rates. The results of the polarization hysteresis loop demonstrate that there is no significant performance loss before and after the wet etching process. A two-step wet etching process of PZT thin film with ultra-low undercut ratio (0.62) is developed. The baseline recipe with a high etch rate, and the selectivity with photoresist is 1.14, and the sidewalls etch into an inclined plane of about 30 degrees. • A new two-step wet etching recipe for PZT film, which use different etchant to etch different phases in PZT film, obtains ultra-low undercut ratio (0.62) and does not generate residual risk, has been developed. • Experimental results have demonstrated that ultra-low undercut, high etch rate, no residual and high selectivity can be simultaneously achieved without using any special processing condition. • Etch results with different acid concentrations in different etchant, processing phenomenon analysis with XRD and TEM, and Interpretation of the etching process and comparison of ferroelectric parameters for the results before and after etching, which can be proven suitability for various etching purposes.

Proposal of oxide-formed two-step wet etching process for n-GaN

We have investigated a wet etching process for n-GaN in order to ultimately develop a low damage and highly controllable etching process that can be applied to device fabrication and which also has the merits of cost and convenience. For this purpose, we propose a GaN oxide-formed two-step wet etching process which consists of (i) the electrochemical oxidation of GaN (anodization), and (ii) the chemical etching of GaN oxide formed in process (i). With this two-step wet etching process, we have successfully performed the wet etching of a patterned area of n-GaN without the aid of light irradiation.

Anisotropic etching on Si{1 1 0}: experiment and simulation for the formation of microstructures with convex corners

We combine experiment, theory and simulation to design and fabricate 3D structures with protected edges and corners on Si{1 1 0} using anisotropic wet chemical etching in 25 wt% tetramethylammonium hydroxide (TMAH) at 71 °C. In order to protect the convex corners formed by <1 1 2 > and <1 1 0 > directions, two methods are considered, namely, corner compensation and two-step etching. The mask design methodology for corner compensation is explained for various microstructures whose edges are aligned along different directions. The detailed geometry of each compensation pattern is shown to depend on the desired etch depth. The two-step wet etching process is explored in order to realize improved sharp convex corners. Using the same etchant concentration and temperature, the second etching is carried out after mask inversion from silicon nitride (Si3N4) to silicon dioxide (SiO2), obtained by local oxidation of silicon (LOCOS) followed by nitride etching. Based on the use of the continuous cellular automaton (CCA), the simulation results for both corner undercutting and two-step etching show that the CCA is suitable for the analysis and prediction of anisotropic etching on Si{1 1 0} wafers.

Integrating Surface Textures on ZnO Substrate for High Light Extraction Efficiency Light-Emitting Diode

Due to the large refractive index of ZnO material, light extraction efficiency (LEE) of ZnO based light-emitting diode (LED) is limited by the total reflection. We present a combined experimental and computational approach to study the effects of integrated surface textures on the efficiency of light extraction from the ZnO material. Hexagonal pyramids and pits textures were obtained by selective and anisotropic etching of O-polarity ZnO single crystal in HCl and KOH solutions, respectively. Dense hexagonal pyramids were integrated into the hexagonal pits via a two-step wet etching process. Ray-tracing simulations indicate that the substrate texturing can improve the performance of the ZnO based LEDs by enhancing the LEE and improving the light field uniformity. The integrated photoluminescence extraction was improved by a factor of 117% with respect to that of a planar ZnO single crystal through integrating the pyramids textures into the hexagonal pits.

Top-Gate Staggered a-IGZO TFTs Adopting the Bilayer Gate Insulator for Driving AMOLED

We report the successful implementation of top-gate staggered amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) with decent performance and environmental stability by adopting the SiOx/SiNx bilayer gate-insulator stack. The PECVD SiOx and SiNx were used as the first and second gate insulators, respectively, in the TFT to simultaneously ensure the channel/gate-insulator interface properties for device performances and the water impermeability of the gate insulator for effective passivation of the channel layer. It was also found that the cleanliness of the back-channel interface (and thus the effectiveness of the source/drain etching process) is critical for the successful implementation of the top-gate staggered a-IGZO TFTs. In this paper, a two-step wet-etching process for source/drain was used to ensure the quality of the back-channel interface. Finally, we successfully integrated the top-gate staggered a-IGZO TFTs into a working 2.2-in active matrix organic light-emitting display panel, demonstrating the real use of the developed TFTs.

A novel process for circle-like 3D microstructures by two-step wet etching

This paper presents a novel technique for developing new structures on a Si substrate used in micro electro mechanical systems. The technique does not require any compensating structure for the fabrication of circle-like 3D microstructures, as reported in the literature. We design a two-step wet etching process and the results show that the application of the technique can lead to an optimal etching process in a more effective manner for the realization of circle-like 3D microstructures, based on a mixture of 5M KOH solution with 20% by volume isopropyl alcohol (IPA) etching at 80 °C for 80 min and then isotropic etching in HF-HNO3 at room temperature for 3 min.

Volume-producible fabrication of a silicon nanowire via crystalline wet etching of (1 1 0) silicon

This study presents a fabrication method of a mass-producible silicon nanowire (SiNW) using a (1 1 0) silicon wafer. Microscale silicon lines, patterned in standard photolithography, are reduced to 300 nm in width in a two-step wet-etching process. The silicon lines are transformed into the SiNW by a thermal oxidation process. The formation of SiNW after thermal oxidation was verified using a numerical oxidation simulation considering the two-dimensional growth of the oxide. After thermal wet oxidation at 970 °C for 50 min, silicon lines of 300 nm in width were transformed into the SiNWs of an inverse triangular cross-section with an effective width of approximately 70 nm. At the same time, the fabricated SiNWs were electrically isolated from the substrate without using an expensive silicon-on-insulator wafer. The pH sensing test, which is usually performed as a preliminary experiment for the biosensor applications, was conducted with respect to various pH solutions. The experimental sensitivity to the pH level was 0.55 nS pH−1, when the voltage applied to the SiNW was 1 V. The SiNW has been completely fabricated by using only a conventional semiconductor process instead of a costly and time-consuming e-beam lithography process for the nanoscale patterning. The proposed fabrication method was successfully confirmed to have the potential of mass-producible and cost-effective SiNW devices for nano-biosensor applications.

Realization of freestanding InP membranes on Si by low-temperature wafer bonding and stress analysis using micro-Raman spectroscopy

We present a method to realize freestanding InP membranes on Si substrate by combination of low-temperature wafer bonding, layer transfer, and wet chemical release processes. The removal of InP substrate and sacrificial etching of an InGaAs layer defines the 2.0μm InP thin layer bonded to Si. The InP membranes are subsequently released by a two-step wet etching process and the surface stress profiling in these freestanding membranes has been carried out by high spectral resolution micro-Raman measurements. Realization of such micromechanical structures on Si platform would be suitable for the integration of InP-based photonic devices on large area Si-based microelectronic systems.

Fabrication of sub-transistor via holes for small and efficient power amplifiers using highly selective GaAs∕InGaP wet etching

We investigated the properties of a citric acid-based GaAs∕InGaP selective wet etchant. We found that the citric acid-based etchant has a much higher selectivity and exhibits less undercutting than those of a conventional sulfuric acid-based etchant that we had used. Then, we applied the citric acid-based wet etchant to the fabrication of via holes with high thermal diffusibility underneath heterojunction bipolar transistors. The citric acid-based etchant exhibited GaAs∕InGaP selectivity of about 9800 at pH 9.0 and enabled reliable etch stopping without pinholes. The citric acid-based etchant also suppressed undercutting and enabled the integration of the via holes. We used the optimized citric acid-based wet etching for finishing the via hole etching after rough high-speed wet etching with the conventional sulfuric acid-based etchant. The two-step wet etching process resulted in a successful fabrication of the sub-transistor via hole structure with collector-up heterojunction bipolar transistors.