Two-point Modulator Research Articles

Self-Calibrated Digital Two-Point Modulator for BLE RF Transmitter

In this brief, a self-calibrated two-point delta-sigma modulation technique for a CMOS RF transmitter is proposed for use for a voltage-controlled oscillator (VCO) and a delta–sigma modulator in a frequency synthesizer. By using the counter to calibrate the frequency deviation of two-point modulation to the desired value, the gain mismatch between two paths can be completely calibrated by modifying the gain of the VCO path. The frequency modulation therefore guarantees a robust performance against PVT variations without using any additional circuit. This technique is applied to Bluetooth Low Energy (BLE) applications. The proposed Two-Point Modulation achieves error vector magnitude (EVM) of −29.3 dB at 1 Mbps and is implemented in 55 nm CMOS process technology. The area of the chip is 0.28 mm2 and its power consumption is 2.9 mW.

A 1.9-mW 750-kb/s 2.4-GHz F-OOK Transmitter With Symmetric FM Template and High-Point Modulation PLL

This paper describes a frequency-domain on-off keying (F-OOK) modulation method which utilizes power detection of both a carrier and a sideband by modulating the carrier frequency with a pre-selected modulation template. Compared to on-off keying and binary frequency-shift keying modulations, more efficient bandwidth control is achieved for the same data rate with a symmetric FM template. Since the proposed modulation maintains the average center frequency of the carrier regardless of data pattern, the F-OOK signal can be generated by using only the high-pass modulation path of the conventional phase-locked loop-based two-point modulator, thus relaxing design complexity. A prototype transmitter implemented in 65-nm CMOS consumes 1.9 mW from a 0.8-V supply with a data rate of 750 kb/s, achieving an energy efficiency of 2.5 nJ/b.

20-Mb/s GFSK Modulator Based on 3.6-GHz Hybrid PLL With 3-b DCO Nonlinearity Calibration and Independent Delay Mismatch Control

A hybrid two-point modulator which mitigates the nonlinearity problem of a digitally controlled oscillator (DCO) and provides a fine delay mismatch calibration is proposed for high data rate applications. A DCO with a separate high-pass modulation path in which only 3 b are used for a capacitor array is designed for flexible gain partition and simple nonlinearity calibration. A nonuniform multilevel quantizer and a finite-impulse response filter are employed to improve modulation quality and reduce quantization noise for high data rate. In the low-pass modulation, a fractional- ${N}$ divider based on a phase rotator and an additional high-frequency $\Delta \Sigma $ modulator enables fine delay time control between two modulation paths. Delay mismatch calibration circuit based on a time-to-digital converter is designed to calculate the optimum delay time automatically. A prototype 3.6-GHz two-point modulator is implemented in 65-nm CMOS. The modulator performs 20-Mb/s GFSK with the error vector magnitude performance of 3.7%, consuming 10.6 mW from a 1-V supply.

A 2 GHz 2 Mb/s Semi-Digital <formula formulatype="inline"><tex Notation="TeX">$2^{+}$</tex></formula>-Point Modulator With Separate FIR-Embedded 1-Bit DCO Modulation in 0.18 <formula formulatype="inline"><tex Notation="TeX">$\mu$</tex> </formula>m CMOS

A 2 GHz two-point modulator which has a separate high-pass control for DCO modulation is implemented in 0.18 μm CMOS. The proposed modulator with the two-path DCO modulation enables a flexible gain partition for the high-pass and low-pass modulation paths within the DCO and relaxes the DCO nonlinearity with 1-b ΔΣ modulation and embedded finite-impulse response (FIR) filtering. A semi-digital ΔΣ PLL with another FIR filtering in the low-pass modulation enhances PLL linearity with a hybrid loop control. The proposed semi-digital modulator achieves 2.03% RMS EVM with 2 Mb/s GFSK modulation, -132 dBc/Hz phase noise at 3 MHz offset, and -80 dBc reference spur.

A Hybrid Loop Two-Point Modulator Without DCO Nonlinearity Calibration by Utilizing 1 Bit High-Pass Modulation

This paper presents a two-point modulator architecture which is immune to the nonlinear effect of the digitally-controlled oscillator (DCO). By utilizing a 1 bit ΔΣ modulation with embedded finite-impulse response (FIR) filtering the high-pass modulation path does not suffer from the DCO gain nonlinearity, thus requiring absolute gain calibration only. The digital FIR filter in the high-pass modulation path not only suppresses quantization noise but also reduces noise coupling with time-interleaved switching of partitioned capacitors. A hybrid FIR filtering method is also employed for the low-pass modulation path to enhance the linearity of the fractional-N phase-locked loop (PLL). A 1.8 GHz two-point modulator based on a semi-digital PLL is implemented in 65 nm CMOS consuming 6.9 mW from a 1 V supply. At the divide-by-2 output frequency of 913.2 MHz, the error-vector magnitude (EVM) values of 1.79% and 1.63% are achieved with 1.08 Mb/s and 270 kb/s GMSK modulation respectively. When the 1.08 Mb/s GFSK modulation is performed with the same PLL parameters, the EVM value of 1.96% is achieved.

A GFSK Transmitter Architecture for a Bluetooth RF-IC, Featuring a Variable-Loop-Bandwidth Phase-Locked Loop Modulator

The use of a two-point modulator with variable PLL loop bandwidth as a GFSK signal generator is proposed. Delta-sigma modulation is adopted for the modulator. Through the combination of a variable PLL feedback loop and delta-sigma modulation, both a fast settling time and very clear eye opening are achieved for the modulator. We fabricate it in 0.35-μm BiCMOS process technology. The two-point modulator has a center-frequency drift of only 14.9 kHz, much lower than the 178-kHz result for a single time slot in the case of direct VCO modulation. This is due to the PLL feedback loop. Evaluation also confirmed that the circuit satisfies the various characteristics required of a Bluetooth transmitter. The two-point modulator is also applicable to other transceivers which use FSK or PSK modulation, i.e. forms of modulation where a constant signal level is transmitted, and thus contributes to the simplification of a range of wireless transmitters.