Two-phase Complementary Pass-transistor Adiabatic Logic Research Articles

Adiabatic Two-Phase CPAL Flip-Flops Operating on Near-Threshold and Super-Threshold Regions

Low-power adiabatic flip-flops operating on near-threshold and super-threshold regions are investigated in this paper. The flip- flops are realized using two-phase CPAL (complementary pass-transistor adiabatic logic) circuits. A traffic light controller operating on near-threshold and super- threshold regions is verified. All circuits are simulated using NCSU PDK 45 nm technology by varying supply voltage from 0.4 V to 0.9 V with 0.1 V steps. Based on the HSPICE simulation results, the energy consumption of the medium-voltage adiabatic flip-flops using two-phase CPAL circuits can be greatly reduced with reasonable speed.

Physical Implementation and Manufacture of Adiabatic Flip-Flops for Micro Power Systems

Flip-flops are main logic cells in digital systems, thus power-efficient designs are essential for micro systems, where ultra low-power hardware is demanded. This paper presents physical implementation and manufacture of adiabatic flip-flops based on CPAL (Complementary Pass-transistor Adiabatic Logic) circuits. The two mode-10 adiabatic counters based on four-phase and two-phase CPAL circuits have been implemented. For comparison, a conventional mode-10 counter using static CMOS circuits has also been embedded in a test chip. Full-custom layouts are drawn, and full parasitic extraction is done. The post-layout simulations are carried out using HSPICE. The chip has been fabricated with Chartered 0.35um process and tested.

Gate-Length Biasing Technique of Complementary Pass-Transistor Adiabatic Logic for Leakage Reduction

Scaling down sizes of MOS transistors has resulted in dramatic increase of leakage currents. To decrease leakage power dissipations is becoming more and more important in low-power nanometer circuits. This paper proposes a gate-length biasing technique for complementary pass-transistor adiabatic logic (CPAL) circuits to reduce sub-threshold leakage dissipations. The flip-flops based on CPAL circuits with gate-length biasing techniques are presented. A traffic light controller using two-phase CPAL with gate-length biasing technique is demonstrated at 45nm CMOS process. The BSIM4 model is adopted to reflect the characteristics of the leakage currents. All circuits are simulated using HSPICE. Simulation results show that the CPAL traffic light controller with the gate-length biasing technique attains 20% to 5% energy savings compared with the one using the original gate length 25MHz to 200MHz.