Two-dimensional Field-effect Transistors Research Articles

Effects of insertion of an h-AlN monolayer spacer in Pt-WSe2-Pt field-effect transistors

The growth of two-dimensional hexagonal aluminum nitride (h-AlN) on transition metal dichalcogenide (TMD) monolayers exhibits superior uniformity and smoothness compared to HfO2\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$_{2}$$\\end{document} on silicon substrate. This makes an h-AlN monolayer an ideal spacer between the gate oxide material and the WSe2 monolayer in a two-dimensional field effect transistor (FET). From first principles approaches, we calculate and compare the transmission functions and current densities of Pt–WSe2–Pt nanojunctions without and with the insertion of an h-AlN monolayer as a spacer in the gate architecture. The inclusion of h-AlN can alter the characteristics of the Pt–WSe2–Pt FET in response to the gate voltage (Vg\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$V_\ ext {g}$$\\end{document}). The FET without (or with) h-AlN exhibits the characteristics of a P-type (or bipolar) transistor: an on/off ratio of around 2.5×106\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$2.5 \ imes 10^{6}$$\\end{document} (or 1.7×106\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$1.7 \ imes 10^{6}$$\\end{document}); and an average subthreshold swing (S.S.) of approximately 109 mV/dec.\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\ ext {dec.}$$\\end{document} (or 112 mV/dec.\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\ ext {dec.}$$\\end{document}), respectively. We observe that Vg\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$V_\ ext {g}$$\\end{document} shifts the profile of the transmission function by an energy of α(eVg)\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\alpha (e V_{\ ext {g}})$$\\end{document}, where α\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\alpha$$\\end{document} represents the gate-controlling efficiency. We observed that αin=83%\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\alpha _{\ ext {in}}=83\\%$$\\end{document} and αout=33%\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\alpha _{\ ext {out}}=33\\%$$\\end{document}, corresponding to whether the Fermi energy is located inside or outside the band gap. Therefore, we construct an effective gate model based on the Landauer formula, with the transmission function at Vg=0\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$V_\ ext {g}=0$$\\end{document} as the baseline. Our model generates results that are consistent with those obtained through first principles calculations. The relative error in current densities between model and first-principles calculations is within [ln(10)S.S.]|ΔVGeff|\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$[\\frac{ln(10)}{S.S.}] | \\Delta V_{\ ext {G}}^{\ ext {eff}} |$$\\end{document}. The 2D atomistic FETs show excellent device specifications and the ability to compete with existing transistors based on traditional silicon technology. Our findings could help advance the design of TMD-based FETs.

Integrated 1D epitaxial mirror twin boundaries for ultrascaled 2D MoS2 field-effect transistors.

In atomically thin van der Waals materials, grain boundaries-the line defects between adjacent crystal grains with tilted in-plane rotations-are omnipresent. When the tilting angles are arbitrary, the grain boundaries form inhomogeneous sublattices, giving rise to local electronic states that are not controlled. Here we report on epitaxial realizations of deterministic MoS2 mirror twin boundaries (MTBs) at which two adjoining crystals are reflection mirroring by an exactly 60° rotation by position-controlled epitaxy. We showed that these epitaxial MTBs are one-dimensionally metallic to a circuit length scale. By utilizing the ultimate one-dimensional (1D) feature (width ~0.4 nm and length up to a few tens of micrometres), we incorporated the epitaxial MTBs as a 1D gate to build integrated two-dimensional field-effect transistors (FETs). The critical role of the 1D MTB gate was verified to scale the depletion channel length down to 3.9 nm, resulting in a substantially lowered channel off-current at lower gate voltages. With that, in both individual and array FETs, we demonstrated state-of-the-art performances for low-power logics. The 1D epitaxial MTB gates in this work suggest a novel synthetic pathway for the integration of two-dimensional FETs-that are immune to high gate capacitance-towards ultimate scaling.

Monolithic three-dimensional integration of complementary two-dimensional field-effect transistors.

The semiconductor industry is transitioning to the 'More Moore' era, driven by the adoption of three-dimensional (3D) integration schemes surpassing the limitations of traditional two-dimensional scaling. Although innovative packaging solutions have made 3D integrated circuits (ICs) commercially viable, the inclusion of through-silicon vias and microbumps brings about increased area overhead and introduces parasitic capacitances that limit overall performance. Monolithic 3D integration (M3D) is regarded as the future of 3D ICs, yet its application faces hurdles in silicon ICs due to restricted thermal processing budgets in upper tiers, which can degrade device performance. To overcome these limitations, emerging materials like carbon nanotubes and two-dimensional semiconductors have been integrated into the back end of silicon ICs. Here we report the M3D integration of complementary WSe2 FETs, in which n-type FETs are placed in tier 1 and p-type FETs are placed in tier 2. In particular, we achieve dense and scaled integration through 300 nm vias with a pitch of <1 µm, connecting more than 300 devices in tiers 1 and 2. Moreover, we have effectively implemented vertically integrated logic gates, encompassing inverters, NAND gates and NOR gates. Our demonstration highlights the two-dimensional materials' role in advancing M3D integration in complementary metal-oxide-semiconductor circuits.

High-performance Schottky-barrier field-effect transistors based on two-dimensional GaN with Ag or Au contacts

The performance of two-dimensional (2D) monolayer GaN Schottky barrier field effect transistors (SBFETs) with four different metals (Ag, Au, Al, and Pt) as electrodes were studied by using ab initio simulations. The N-type Schottky contact is formed on Ag-GaN, Au-GaN, and Pt-GaN, characterized by electron Schottky barrier heights (SBH) of 0.6, 0.5, and 0.38 eV, respectively. Whereas, Al-GaN contact formed P-type Schottky contact with hole SBH of 1.42 eV. The 5.1 nm GaN SBFETs with four metal electrodes all could overcome the short-channel effect. Additionally, GaN SBFETs with Ag and Au electrodes have excellent performance, whose ON-currents are 1151.1 μA/μm and 1258.9 μA/μm, respectively. They could satisfy the demands of International Technology Roadmap for Semiconductors for high-performance transistor. Furthermore, research indicates that the device's current increases with increasing temperature. Notably, under the constant bias and gate voltage, the current is unaffected by temperature variations between the left and right electrodes.

Low-Power Transistors with Ideal p-type Ohmic Contacts Based on VS2/WSe2 van der Waals Heterostructures.

Achieving low-resistance Ohmic contacts with a vanishing Schottky barrier is crucial for enhancing the performance of two-dimensional (2D) field-effect transistors (FETs). In this paper, we present a theoretical investigation of VS2/WSe2-vdWHs-FETs with a gate length (Lg) in the range of 1-5 nm, using ab initio quantum transport simulations. The results show that a very low hole Schottky barrier height (-0.01 eV) can be achieved with perfect band offsets and reduced metal-induced gap states (MIGS), indicating the formation of p-type Ohmic contacts. Additionally, these FETs also exhibit an impressive low subthreshold swing (SS) (69 mV/dec) and high Ion/Ioff (>107) with an appropriate underlap (UL) structure consisting of pristine WSe2. Furthermore, even when the Lg is scaled down to 3 nm, the device can still meet the low-power (LP) requirements of the International Technology Roadmap for Semiconductors (ITRS) by controlling the UL. Consequently, this study provides valuable insights for the future development of LP 2D FETs.

Anti-ambipolar transport and logic operation in two-dimensional field-effect transistors using in-series integration of GeAs and SnS2

Germanium arsenide (GeAs) from the IV–V semiconductor family has drawn attention for its anisotropic optical and electrical characteristics as a robust p-type semiconductor with high mobility. Despite its potential, the scope of applications for two-dimensional (2D) GeAs remains limited. In this study, we investigate the in-series integration of GeAs and SnS2 for complementary inverter operation, a crucial element in logic circuits. Moreover, the resulting in-series field-effect transistors reveal a previously undocumented anti-ambipolar behavior in this configuration, with a peak-to-valley ratio exceeding 5000 at a drain-source bias of 2 V. This anti-ambipolar characteristic operates regardless of the direction of current flow, which is rarely seen in conventional anti-ambipolar transistors built with hetero-stacked p–n junctions. Moreover, the in-series structure demonstrates stable operation as a complementary inverter, highlighting the versatile potential of p-type 2D GeAs in diverse optoelectronic applications. This work contributes insights into the transport characteristics of GeAs and its interconnected arrangement with SnS2, offering valuable implications for the development of advanced 2D material-based devices.

Three-dimensional integration of two-dimensional field-effect transistors.

In the field of semiconductors, three-dimensional (3D) integration not only enables packaging of more devices per unit area, referred to as 'More Moore'1 but also introduces multifunctionalities for 'More than Moore'2 technologies. Although silicon-based 3D integrated circuits are commercially available3-5, there is limited effort on 3D integration of emerging nanomaterials6,7 such as two-dimensional (2D) materials despite their unique functionalities7-10. Here we demonstrate (1) wafer-scale and monolithic two-tier 3D integration based on MoS2 with more than 10,000 field-effect transistors (FETs) in each tier; (2) three-tier 3D integration based on both MoS2 and WSe2 with about 500 FETs in each tier; and (3) two-tier 3D integration based on 200 scaled MoS2 FETs (channel length, LCH = 45 nm) in each tier. We also realize a 3D circuit and demonstrate multifunctional capabilities, including sensing and storage. We believe that our demonstrations will serve as the foundation for more sophisticated, highly dense and functionally divergent integrated circuits with a larger number of tiers integrated monolithically in the third dimension.

Monolayer SnS2 Schottky barrier field effect transistors: effects of electrodes.

Achieving Ohmic contacts with low resistance is quite desirable for two-dimensional (2D) Schottky barrier field effect transistors (SBFETs). We verify the electrode effect on monolayer (ML) SnS2 SBFETs using ab initio calculations. With the aforeselected ML electrodes from matching lattices and work functions, we obtain n-type Ohmic contacts or quasi-Ohmic contacts to ML SnS2 with ML 1T-NbTe2, Sc2NF2, Mo2NF2, Nb2CF2, and graphene electrodes. The n-type ML SnS2 SBFET with the Ohmic-contact 1T-NbTe2 electrode exhibits remarkably better device performance than that with a Schottky-contact 2H-NbTe2 electrode, and their on-state currents of 629/1048 μA μm-1, delay times of 0.236/0.169 ps, and power dissipations of 0.074/0.089 fJ μm-1 exceed the International Roadmap for Devices and Systems targets for low-power/high-performance application. This study reports on Ohmic-contact electrodes for n-type ML SnS2 SBFETs and can give hints for future theoretical and experimental studies on 2D SBFETs.

Two-Dimensional Ternary Nanocomposite-Decorated Cellulose Field Effect Transistor for Nonenzymatic Sweat Glucose Sensing

Two-Dimensional Ternary Nanocomposite-Decorated Cellulose Field Effect Transistor for Nonenzymatic Sweat Glucose Sensing

Toward High-Performance p-Type Two-Dimensional Field Effect Transistors: Contact Engineering, Scaling, and Doping.

n-type field effect transistors (FETs) based on two-dimensional (2D) transition-metal dichalcogenides (TMDs) such as MoS2 and WS2 have come close to meeting the requirements set forth in the International Roadmap for Devices and Systems (IRDS). However, p-type 2D FETs are dramatically lagging behind in meeting performance standards. Here, we adopt a three-pronged approach that includes contact engineering, channel length (Lch) scaling, and monolayer doping to achieve high performance p-type FETs based on synthetic WSe2. Using electrical measurements backed by atomistic imaging and rigorous analysis, Pd was identified as the favorable contact metal for WSe2 owing to better epitaxy, larger grain size, and higher compressive strain, leading to a lower Schottky barrier height. While the ON-state performance of Pd-contacted WSe2 FETs was improved by ∼10× by aggressively scaling Lch from 1 μm down to ∼20 nm, ultrascaled FETs were found to be contact limited. To reduce the contact resistance, monolayer tungsten oxyselenide (WOxSey) obtained using self-limiting oxidation of bilayer WSe2 was used as a p-type dopant. This led to ∼5× improvement in the ON-state performance and ∼9× reduction in the contact resistance. We were able to achieve a median ON-state current as high as ∼10 μA/μm for ultrascaled and doped p-type WSe2 FETs with Pd contacts. We also show the applicability of our monolayer doping strategy to other 2D materials such as MoS2, MoTe2, and MoSe2.

A drain current formula for two-dimensional field-effect transistors with one-shot convergence algorithm

Two-dimensional material-based field-effect transistors (2DM-FETs) exhibit both ambipolar and unipolar carrier transports. To physically and compactly cover both cases, a quasi-Fermi-level phase space (QFLPS) approach was proposed, but it still involves complicated integration operations. This article aims at improving the numerical efficiency of the QFLPS model by several orders of magnitude so that it can readily be implemented in a standard circuit simulator. We first rigorously derive the integral-free formula for the drain-source current to achieve this goal. Besides computationally benign, it explicitly gives the correlation terms between the electron and hole components. Secondly, to work out the boundary values required by the new expressions, we develop an algorithm for the channel electrostatic potential based on the zero-temperature limit property of the 2DM-FET system. By calibrating the model with the realistic device data of black phosphorus and monolayer molybdenum disulfide FETs, the algorithm is tested against practical cases. Two orders of magnitude improvement in time consumption can be achieved compared with the integral-form QFLPS approach, and it is even four orders of magnitude faster than the traditional continuity-equation based approach.

Nanoforming of transferred metal contacts for enhanced two-dimensional field effect transistors

Nanoforming of transferred metal contacts for enhanced two-dimensional field effect transistors

Two-dimensional α-In2Se3 field effect transistor for wide-band photodetection and non-volatile memory

Mechanically exfoliated two-dimensional α-In2Se3 flakes are used as the channel material in field effect transistors. N-type conduction with 0.14cm2Vs carrier mobility is reported. The good gate modulation and the pronounced hysteresis make the device suitable for a wide range of applications, from digital logics to memories. An order of magnitude current increase is observed under illumination by a blue light at the incident optical power of 19 nW. The devices can work as visible-to-infrared wide-band photodetectors with time response of few-hundred milliseconds, responsivity up to 40A/W and specific detectivity D*=5⋅1011Jones at low light intensity.

Realization of Fermi level unpinning and high-quality p-type contacts for 2D β-TeO2 by a built-in intercalation

Contriving an industry-compatible method for fabricating purely high-quality p-type two-dimensional (2D) field effect transistors (FETs) has been proved to be pressing but challenging due to the strong interfacial coupling and thus tight Fermi level pinning (FLP). Herein, by employing density functional theory calculations, a straightforward but effective strategy is proposed to achieve high-quality p-type contact in few-layer TeO2–Pt junction by using a build-in intercalation to suppress the FLP and shield the damage from electrodes to the excellent electrical properties of TeO2 such as its ultra-high hole mobility. Specifically, the increase of TeO2 layer number will make the charge distribution of VBM and CBM be more lumped in the inner core layer, as a result, the outlying Te–O sublayer can act as an inserting layer like BN to protect the semiconducting electronic states and avoid gap-state pinning. Thus, as the TeO2 layer increases from 1 L to 3 L, (Ⅰ) strong FLP in metal-TeO2 interfaces is gradually unpinned; (Ⅱ) the polarity of Pt–TeO2 contact reverses from n-type to p-type; (Ⅲ) the excellent electrical properties of TeO2 such as hole effective mass is preserved as original despite strong charge transfer occurring at the interface. Besides, the tunnelling barrier at the interface is close to zero. This is quite different from introducing an extern BN intercalation, in which case the tunnelling through BN will prominently reduce the overall hole current. In addition, the contacts between 2D metal electrodes and monolayer TeO2 are found to obey the Schottky-Mott rule, and thereby p-type Ohmic contacts can be obtained at TeO2-VS2, -NbS2 interfaces. Whereas, a relatively large tunnelling barrier exists at the 2D metal-TeO2 interfaces. Our findings are quite essential and beneficial for designing high-performance p-type 2D FETs.

ReS2 Nanosheet-Based Channels for Two-Dimensional Field Effect Transistors and Phototransistors with High Photoresponsivity

ReS₂ Nanosheet-Based Channels for Two-Dimensional Field Effect Transistors and Phototransistors with High Photoresponsivity

Advances in atomic layer deposited high-κ inorganic materials for gate dielectrics engineering of two-dimensional MoS2 field effect transistors

Advances in atomic layer deposited high-κ inorganic materials for gate dielectrics engineering of two-dimensional MoS2 field effect transistors

Oxidation of tantalum disulfide (TaS2) films for gate dielectric and process design of two-dimensional field-effect device

Ta-based high-κ dielectrics can be synthesized via the oxidation of TaS2 films. In this study, we investigated the wet and dry oxidation of TaS2 films via thermal annealing and plasma irradiation, respectively. The specific vibration observed via Raman spectroscopy, the bonding states observed via x-ray photoelectron spectroscopy, and capacitance measurements confirmed the oxidation of TaS2 films with a dielectric constant of ∼14.9. Moreover, the electrical transport of the TaS2 films along the in-plane direction indicated a change in conductivity before and after the oxidation. The thickness of the oxidized film was estimated. Accordingly, the layer-by-layer oxidation was limited to approximately 50 nm via plasma irradiation, whereas the TaS2 films within 150 nm were fully oxidized via thermal annealing in ambient air. Therefore, a Ta-oxide/TaS2 structure was fabricated as a stack material of insulator and metal when the thickness of the pristine film was greater than 50 nm. In addition, Ta-oxide films were integrated into bottom-gated two-dimensional (2D) field-effect transistors (FETs) using the dry transfer method. 2D FETs with multilayer MoTe2 and MoS2 films as p-type and n-type channels, respectively, were successfully fabricated. In particular, the Ta-oxide film synthesized via dry oxidation was used as a gate dielectric, and the device process could be simplified because the Ta-oxide/TaS2 heterostructure can function as a stack material for gate insulators and gate electrodes. An anti-ambipolar transistor consisting of an MoTe2/MoS2 heterojunction was also fabricated. For the transfer characteristics, a relatively sharp on-state bias range below 10 V and sufficiently high peak-to-valley ratio of 106 at V DS = 3 V were obtained using the high-κ gate dielectric of Ta-oxide despite the presence of the multilayer channels (∼20 nm).

Quasi-Fermi-Level Phase Space and its Applications in Ambipolar Two-Dimensional Field-Effect Transistors

Quasi-Fermi levels (QFLs) have become a canonical concept in semiconductor device modeling. However, a global model to cover both unipolar and ambipolar transport modes of two-dimensional field-effect transistors (2D FETs) based on QFLs is still needed, as it is challenging to capture quantitatively the effect of QFL splitting on transport. This work establishes a theoretical platform to account for that effect: the quasi-Fermi-level phase space (QFLPS). With QFLPS a unified picture of unipolar and ambipolar transport is drawn, the working modes of 2D FETs acquire more intuitive physical interpretations, and many valuable outcomes for device modeling and circuit design are realized.

Performance Enhancement of SnS/h-BN Heterostructure p-Type FET via the Thermodynamically Predicted Surface Oxide Conversion Method.

Searching for the counterpart of well-developed two-dimensional (2D) n-type field effect transistors (FETs) is indispensable for complementary logic circuit applications for 2D devices. Although SnS is regarded as a potential candidate for high-performance p-type FETs, recent experiments only show poor results deviating from the theoretically predicted high mobility. In this research, the serious performance degradation due to the surface oxidation of SnS, which commonly occurs in most 2D materials, is addressed through surface oxide conversion using highly reactive Ti. In this conversion process, which is confirmed by systematic characterization, the reduction of SnS surface oxide is accompanied by the formation of functional titanium oxide, which works as both a conductive intermediate layer to improve the contact property and a buffer layer of the high-k top gate insulator at the channel region. Consequently, a record-high field effect mobility of 87.4 cm2 V-1 s-1 in SnS p-type FETs is achieved. The surface oxide conversion method applied here is consistent with our previous thermodynamic prediction, and this novel technique can be widely introduced to all 2D materials that are vulnerable to oxidation and facilitate the future development of 2D devices.

Clean BN-Encapsulated 2D FETs with Lithography-Compatible Contacts.

Device passivation through ultraclean hexagonal BN encapsulation has proven to be one of the most effective ways of constructing high-quality devices with atomically thin semiconductors that preserve the ultraclean interface quality and intrinsic charge transport behavior. However, it remains challenging to integrate lithography-compatible contact electrodes with flexible distributions and patterns. Here, we report the feasibility of a straightforward integration of lithography-defined contacts into BN-encapsulated two-dimensional field-effect transistors (2D FETs), giving rise to overall device quality comparable to the state-of-the-art results from the painstaking pure dry transfer processing. The electronic characterization of FETs consisting of WSe2 and MoS2 channels reveals an extremely low scanning hysteresis of ∼2 mV on average, a low density of interfacial charged impurities of ∼1011 cm-2, and generally high charge mobilities over 1000 cm2 V-1 s-1 at low temperatures. The overall high device qualities verify the viability of directly integrating lithography-defined contacts into BN-encapsulated devices to exploit their intrinsic charge transport properties for advanced electronics.