Turbo Product Codes Research Articles

Efficient turbo product code decoder with Build‐In SRAM‐based transpose memory

AbstractTurbo product codes (TPCs) have been widely used for bit error correction in high‐speed applications such as data storage. This letter introduces an efficient hard‐input hard‐output iterating TPC decoder module. A transpose memory utilizing static random access memory (SRAM) is integrated into the decoder to achieve a low hardware overhead. The transpose memory, based on an 8T SRAM bit‐cell, supports both horizontal (row‐wise), and vertical (column‐wise) read/write operations. It is prototyped under a 28nm high‐k/metal gate stack process with bit‐cell size of 0.582 µm2. This specialized SRAM significantly reduces the hardware overhead when compared with a register‐array‐based transpose memory without significant throughput loss. A field programmable gate array (FPGA) evaluation platform is utilized to emulate the TPC decoder module, and the maximum decoder throughput is up to 6.49 Gbps at 250 MHz.

An Adaptive Chase-Pyndiah Algorithm for Turbo Product Codes

The Chase-Pyndiah algorithm is a soft decoding algorithm for turbo product codes (TPCs) with promising error correction performance. In this letter, we propose an adaptive Chase-Pyndiah algorithm to improve the error correction performance for TPCs with negligible complexity increase. The proposed algorithm adaptively adjusts the weighting factor and reliability factor according to the analog weight of the decision codeword for a component code. Simulation results show that the proposed algorithm can achieve a signal-to-noise ratio (SNR) gain of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.16\sim 0.18$ </tex-math></inline-formula> dB at the bit-error-rate (BER) of 10−6 over additive white Gaussian noise (AWGN) channels.

Real-Time FPGA Investigation of Potential FEC Schemes for 800G-ZR/ZR+ Forward Error Correction

Forward error correction (FEC) performance down to 1e-15 bit error rate (BER) of a open FEC code (OFEC), which was recently proposed for the 800G inter-data center interconnect (DCI) standard, is verified with a 100-piece-FPGA implementation at a record 400-Gbps throughput. Besides the OFEC, we also investigate the cons and pros of the concatenated staircase and Hamming code (CFEC) and multilevel codes (MLC) of a concatenated Low-Density Parity-Check (LDPC) and Turbo Product Code (TPC), which are the candidate schemes for the 800G-ZR FEC. The OFEC performance as a function of decoding iterations of Soft-in Soft-out (SISO) and Hard-in Hard-out (HIHO) is investigated, and FPGA emulations reveal the existence of an error flare of the OFEC with two SISO iterations and an severe error floor with one HIHO iteration even with four SISO iterations. Further investigations on different combinations of SISO and HIHO iterations, revealed that three SISO and two HIHO iterations are the optimal choice. Based on this iteration configuration, we studied the methods that decreasing the test patterns (TP) of SISO decoder and the soft bits to reduce the implementation complexity. Then we proposed the simplified OFEC scheme for 800G-ZR application, providing 1.81e-2 pre-FEC BER threshold with half power dissipation of standard OFEC, achieving a trade-off between the error correction performance and power dissipation. Finally, we investigated the performance of performance enhanced OFEC with 24.3% overhead and 2.5e-2 pre-FEC threshold, and finally, FEC candidates for the 800G-ZR+ applications are studied, indicating that the OFEC and channel polarized multilevel coding (CP MLC) are the most promising schemes.

Efficient Decoder for Turbo Product Codes Based on Quadratic Residue Codes

In this letter, we study turbo product codes with quadratic residue codes (called QR-TPCs) as the component codes. We propose an efficient decoder based on Chase-II algorithm with two convergence conditions for the iterative decoding of QR-TPCs. For each row and column, the Chase-II decoder will stop immediately when one of the conditions is met. The simulation results show that the proposed algorithm has a lower computational complexity compared with existing decoding methods. Moreover, a comparison with 5G low-density parity-check codes shows that the proposed turbo product codes have better performance for short code lengths.

An improved Chase–Pyndiah algorithm in the iterative decoding of turbo product codes

This paper considers the design of turbo product codes (TPCs) for short and bursty packages, which is suitable for low latency machine-to-machine type communication. A new soft syndrome-based approach is proposed to compute the weighting factors in the iterative Chase–Pyndiah decoding of TPCs. A new soft syndrome estimation method is developed which has a manageable computational complexity. Numerical results show that the bit error rate performance is improved by using this simple approach for short package sizes for TPCs with high coding rates.

Turbo Product Codes for Satellite Communication: a Survey

Turbo Product Codes (TPCs) with near Shannon capacity performance especially for high code rates allow decoding operations at a speed of several Mbps or more and has low error floor. In this paper, the characteristics of TPCs as FEC code, and their suitability for being a potential candidate in satellite communication applications are discussed. Emphasis is laid to highlight TPC's flexibility in attaining different code rates, improved coding gain especially for high code rates, benefits of different types of TPC construction and decoding modifications. The need for careful amalgamation of higher order modulation techniques with TPCs to achieve good spectral and power efficiency is discussed in detail. In addition, a deep learning based approach (neural-BP) for decoding of TPCs has been discussed. This is intended to improve the parallelism in TPC decoding and to reduce the implementation complexity. It is envisaged that the neural-BP decoding approach would lead to the design of hardware efficient decoders providing high Quality of Service (QoS) in satellite communication systems.

Intelligent Equalization Based on RBF LSSVM and Adaptive Channel Decoding in Faster-than-Nyquist Receiver

On one hand, aiming at the prominent problem of improving the reliability of Faster-than-Nyquist (FTN) wireless transmission, abandoning the channel estimation, we propose the Radial Basis Function Least Squares Support Vector Machine (RBF LSSVM) algorithm based on Intelligent Signal Processing for FTN equalization and form FTN time domain transverse filter equalizer. The model of FTN wireless communication system based on equalization of LSSVM algorithm is established by adding 50-bit training sample sequence module. On the other hand, in the FTN transmission BPSK modulation system receiving terminal, we propose joint research equalization of LSSVM algorithm and adaptive channel decoding scheme of Chase algorithm, to improve the reliable transmission performance of FTN wireless communication. The threshold value is 20, and the adaptive 2-D Turbo Product Codes (TPC) encoding and decoding is simulated by four iterations. The BER performance of FTN wireless communication combined with LSSVM algorithm and TPC adaptive decoding is simulated.

A Parallel Transmission Scheme Based on the Turbo Product Code for Through Silicon via Array in Three-Dimensional Integrated Circuits

Through silicon via (TSV) is the key technology for the vertical interconnect in three-dimensional integrated circuits (3-D ICs). With the help of TSVs, higher throughput in signal transmission can be attained. However, the tightly clustered TSVs in the TSV array suffer from crosstalk noise, a situation which results in transmission errors. This study investigates, the channel model of the TSV array, involving main factors affecting transmission performance, such as transmission loss, inter-channel interference, and crosstalk noise with different digital patterns. A parallel transmission scheme based on a turbo product code (TPC) parallel coding is proposed. In this scheme, the binary bits of information are reshaped into two dimensional blocks. Each block is parallel encoded using a TPC into a codeword block for parallel transmission through the TSV array channel. At the receiver, the sending information is reformed by a concurrent hard decision decoding algorithm of a TPC. This parallel transmission scheme achieves low bit-error-rate, high throughput, and a lower system overhead relative to that of its ground TSV shielded counterpart if the type of TPC is carefully selected. The simulation results confirm that this scheme reduces inter-symbol interference, minimizes structural defects in the TSV array, and improves transmission performance in 3-D ICs.

Iterative Decoding of Chase Pyndiah Decoder Utilizing Multiple Relays Network

In this paper, a distributed Encoding and decoding of Turbo Product Code (TPC) over single and multiple relays network are proposed. The information message matrix is encoded at source by Bose Chaudhuri Hochquenghem (BCH) as component code and transmitted to destination and relays in the midway between source and destination. The coded source message is decoded by simple chase П decoder at relay and encoded again horizontally and vertically by BCH component code to construct TPC. Two scenarios were investigated. First scenario, utilizing one relay in cooperative network, where the vertical parity part of TPC is transmitted to destination to be the input of row decoder for original chase pyndiah decoder, while the received encoded horizontally matrix from source is the input of the column decoder. In the second scenario multiple relays are utilized and multiple copies of vertical parity part of TPC are sent to destination to be decoded by the proposed modified iterative chase pyndiah decoder with multiple integrated stages for each iteration. Simulation results for the first scenario over Additive White Gaussian (AWGN) and Rayleigh fading channels and using original chase Pyndiah decoder at destination shows 2dB gain improvement at BER= 〖10〗^(-5) and 4dB gain improvement at BER=〖10〗^(-4) respectively over BER performance of un cooperative system. While results for distributed TPC decoding for the second scenario and using the proposed modified iterative chase Pyndiah decoder at destination shows 2.7 dB and 3 dB gain at BER =〖10〗^(-4) for AWGN and Rayleigh fading channels respectively over the first scenario.

Hard Decision Decoding Performance Improved Using Turbo Product Codes

The performance of soft decision decoding, whose for which the design is complex, is superior to the performance of hard decision decoding. In this paper, we propose a turbo product code with a bit flip algorithm to improve the performance of hard decision decoding. The performance of hard decision decoding is improved with low complexity using multidimensional turbo product codes. The reliability of decoding in a communication system to detect and correct errors is discussed .Maximum a posterior probability (MAP) decoding is employed to improve the hard decision performance of turbo product codes with multiple dimensions. Our results include comparisons of multiple dimensions—2D, 3D, 4D, and 5D—and the number of iterations in soft and hard decision decoding.

Ultra-Light Decoder for Turbo Product Codes

This letter presents a novel low-complexity decoder for turbo product codes (TPCs). The new decoder, denoted as ultra-light decoder (ULD), can perform soft-decision decoding without an algebraic hard decision decoder, which is the core of conventional soft-decision decoders of block codes. Moreover, the unique structure of the ULD enables the design of a new approach to compute the minimum Euclidean distance at each decoding iteration. Therefore, the ULD offers significant complexity and delay reduction as compared with the conventional TPC decoders. Reducing the complexity and delay will enable using codes with high code rates to improve the system spectral efficiency or use powerful codes with low code rates to reduce the transmission power. The system bit-error rate is presented for binary and $M$ -ary modulation schemes over additive white Gaussian noise channels, and the coding gain is given for Rayleigh fading channels. The obtained numerical results show that the ULD offers coding gain that is comparable to the conventional TPC decoders under various system and channel conditions but with significantly lower complexity.

TPC Together with Overlapped Time Domain Multiplexing System Based on Turbo Structure

Overlapped time domain multiplexing (OvTDM) is a novel technique for utilizing inter-symbol interference (ISI) to benefit a communication system. We implement the OvTDM technique based on turbo structure and associate a turbo product code (TPC) to construct a novel coded turbo-structure OvTDM system. Two schemes of the iterative receiver and soft-input and soft-output (SISO) decoding algorithms are presented. Simulation results show an attractive advantage and performance of designed structures.

On the Error Performance of Coding and Equalization in Low-Complexity Ultra-Wideband Communication Systems

In this paper, the performance of various channel coding schemes is investigated in pulse-based ultra-wideband(UWB) communication systems for applications in short-range indoor environments. Pulse-based binary (BPSK) modulation and decision-feedback equalization (DFE) is considered. Concatenated adaptive equalization and coding is explored as an alternative to the more complex and often impractical joint coding and equalization. A block length of approximately 1000 bits is considered in this paper as it results in a static channel with minimal latency while still yielding relatively good error performance. The error performance of a previously proposed turbo product code (TPC), based on two identical Hamming (31,26) codes, is simulated and compared with that of otherchannel coding schemes of similar rate and code length. These include a regular LDPC (1057,813) code, a memory-6 rate-3/4 punctured convolutional code, a Reed-Solomon (127,89) code and a concatenated (off-the-shelf) code with a Reed-Solomon (255,239) outer code and a memory-6 rate-3/4 punctured convolutional inner code. The inclusion of the concatenated Reed-Solomon scheme serves as a reference, as this is an off-the-shelf classical and still popular solution. The simulation results show that, among the coding schemes considered, the LDPC code offers the best error performance.

A construction of quantum turbo product codes based on CSS-type quantum convolutional codes

As in classical coding theory, turbo product codes (TPCs) through serially concatenated block codes can achieve approximatively Shannon capacity limit and have low decoding complexity. However, special requirements in the quantum setting severely limit the structures of turbo product codes (QTPCs). To design a good structure for QTPCs, we present a new construction of QTPCs with the interleaved serial concatenation of [Formula: see text]-type quantum convolutional codes (QCCs). First, [Formula: see text]-type QCCs are proposed by exploiting the theory of CSS-type quantum stabilizer codes and QCCs, and the description and the analysis of encoder circuit are greatly simplified in the form of Hadamard gates and C-NOT gates. Second, the interleaved coded matrix of QTPCs is derived by quantum permutation SWAP gate definition. Finally, we prove the corresponding relation on the minimum Hamming distance of QTPCs associated with classical TPCs, and describe the state diagram of encoder and decoder of QTPCs that have a highly regular structure and simple design idea.

Single Parity Check 부호를 적용한 3차원 Turbo Product 부호의 효율적인 복호 알고리즘

본 논문에서는 single parity check 부호(SPC)를 포함하는 3차원 turbo product 부호(TPC)의 효율적인 복호 기법을 제안한다. 일반적으로 TPC의 부호율을 극대화하기 위한 목적으로 부호 길이가 짧은 축에서 SPC 부호를 적용한다. 그러나 SPC 부호가 오류 정정 능력이 없는 부호이기 때문에 3차원 TPC를 Chase-Pyndiah 복호 알고리즘만으로 복호할 경우, 2차원 TPC에 비하여 성능 개선이 거의 발생하지 않는다. 본 논문에서는 이를 개선하기 위해 다음의 2가지 기법을 복호 과정에 적용하였다. 우선 SPC 부호로 이루어진 축에서는 구현 복잡도를 낮추기 위하여 <TEX>$min^*$</TEX>-sum 알고리즘을 복호 방법으로 적용하였으며, 반복 복호 방식으로는 성능 개선을 위해 직렬 복호 방식을 변형한 방식을 이용하였다. 마지막으로 이를 적용한 TPC 시뮬레이터의 성능을 비교 분석하고, 실제 하드웨어 구현과정에서 고려해야 할 부분을 소개한 후, VHDL을 이용하여 3차원 TPC를 설계하였다. In this paper, we propose a decoding scheme that can apply to a three dimensional turbo product code(TPC) with a single parity check code(SPC). In general, SPC is used an axis with shortest code length in order to maximize a code rate of the TPC. However, SPC does not have any error correcting capability, therefore, the error correcting capability of the three-dimensional TPC results in little improvement in comparison with the two-dimensional TPC. We propose two schemes to improve performance of three dimensional TPC decoder. One is <TEX>$min^*$</TEX>-sum algorithm that has advantages for low complexity implementation compared to Chase-Pyndiah algorithm. The other is a modified serial iterative decoding scheme for high performance. In addition, the simulation results for the proposed scheme are shown and compared with the conventional scheme. Finally, we introduce some practical considerations for hardware implementation.

Turbo Product Codes: Applications, Challenges, and Future Directions

Turbo product codes (TPCs) have been integrated in several practical applications, and hence, they have been considered widely in the literature where the main aim is improving the error performance and/or reducing the computational and implementation complexity. This paper presents a comprehensive survey of the research that focuses on TPCs in terms of encoding, decoding, error performance, and complexity. Moreover, this paper also considers the advantages of integrating TPCs in hybrid automatic repeat request systems where power optimization becomes very efficient and the complexity can be reduced using the unique properties of TPCs such as error self-detection capabilities. Based on the surveyed literature, the pivotal open research issues in TPCs are presented and discussed.

Constrained Turbo Product and Block-Convolutional Codes in Wireless Applications

Constrained interleavers are used in constrained turbo product codes (CTPCs) and constrained turbo block-convolutional (CTBC) codes. The constrained interleaver delivers an interleaver gain close to uniform interleaving while also increasing the minimum Hamming distance. In this study, new and improved single row (SR) versions of the previous codes, called SR-CTPCs and SR-CTBC codes, are introduced that have higher interleaver gain, better performance, and much more flexible frame sizes as needed in wireless applications. Compared with the WiMax and the long-term evolution standards, it is demonstrated that SR-CTPC and SR-CTBC codes perform better than those currently used in the wireless standards.

Shortening the Turbo Codes Based on Unequal Error Protection

Shortened turbo product codes (TPCs) have already been adopted in many standards, especially in multimedia field. Generally, the realizations of shortening turbo codes are based on designing specific interleavers with variable interleaving span; or using shortened–extended Hamming codes as the component to obtain different encoding block sizes. In this paper, we propose a very simple method to realize the shortening. This method is based on a parallel concatenated convolutional code (PCCC) and their inherent characteristic of unequal error protection. Sample simulation results are presented confirming the efficiency of the proposed scheme.

Transmission Performance of 4D 128SP-QAM With Forward Error Correction Coding

The performance of the 4-D 128SP-QAM format is experimentally investigated in a Nyquist-wavelength division multiplexing system for two different forward error correction (FEC) scenarios. Two soft-decisions FEC schemes are experimentally evaluated for 128SP-QAM, namely, a turbo product code (TPC) and a low-density parity-check (LDPC) code. The results show that after full convergence the LDPC code outperforms the TPC with respect to coding gain at a bit error ratio of $10^{\mathrm {\mathbf {-8}}}$ . However, it requires more decoding iterations to achieve convergence toward an optimum performance state.

Low Complexity Power Optimization Algorithm for Multimedia Transmission Over Wireless Networks

This paper considers the problem of transmit power optimization for multimedia applications in continuous high-speed transmission over wireless networks. The power optimization process is developed by noting that some performance metrics such as throughput, delay and peak signal-to-noise ratio (PSNR) for particular systems with hybrid automatic repeat request (HARQ) may exhibit a staircase behavior. In such scenarios, the corresponding metric remains fixed for a wide range of signal-to-noise ratios (SNRs). Consequently, the transmit power can be reduced significantly while the relevant metric remains almost unchanged. The obtained results reveal that invoking power optimization algorithms can achieve a significant power saving of about 80% for particular scenarios. The system considered in this work is a truncated HARQ with turbo product codes (TPC) and parallel concatenated convolutional codes (PCCC). Chase combining is also used to combine the retransmitted packets with the original transmission. An efficient semi-analytical model is developed to obtain the system throughput in additive white Gaussian noise (AWGN) and Rayleigh fading channels. The obtained results also show that using the throughput, delay or PSNR as performance metrics provides equivalent power saving results.