Turbo Decoding Message Passing Research Articles

Analysis of TDMP Algorithm of LDPC Codes Based on Density Evolution and Gaussian Approximation.

Based on density evolution analysis of the existing belief propagation (BP) algorithm, the Turbo Decoding Message Passing (TDMP) algorithm was analyzed from the perspective of density evolution and Gaussian approximation, and the theoretical analysis process of TDMP algorithm was given. When calculating the prior message of each layer of the TDMP algorithm, the check message of the previous iteration should be subtracted. Therefore, the result will not be convergent, if the TDMP algorithm is directly analyzed based on density evolution and Gaussian approximation. We researched the TDMP algorithm based on the symmetry conditions to obtain the convergent result. When using density evolution (DE) and Gaussian approximation to analyze the decoding convergence of the TDMP algorithm, we can provide a theoretical basis for proving the superiority of the algorithm. Then, based on the DE theory, we calculated the probability density function (PDF) of the check-to-variable information of TDMP and its simplified algorithm, and then gave it a calculation based on the process of the normalization factor. Simulation results show that the decoding convergence speed of the TDMP algorithm was faster and the iterations were smaller compared to the BP algorithm under the same conditions.

The Research on TDMP Merged Decoding Algorithm of LDPC Codes Based on DVB-S2 Standard

DVB-S2 is the second generation of Digital Video Broadcasting-Satellite and LDPC (Low Density Parity Code) is the key technology in which the decoding plays an important role in determining the performance of DVB-S2 system. According to the research on the characteristics of DVB-S2 standard, this paper reports on the improvement of the Turbo Decoding Message Passing (TDMP) algorithm by adopting the idea of merging. The component codes which don’t have public nodes are regarded as a new component. By changing the decoding order of component codes and removing useless waiting time, the message capacity transmitted between two adjacent component codes is increased. The performance of the proposed TDMP merged decoding algorithm is evaluated by simulation experiments. We measure decoding performance, convergence rate and the average decoding time to evaluate the system performance. The results obtained show that the TDMP merged decoding algorithm ensures the performance of decoding and good convergence, and also improves the average decoding speed and throughput.

Design of a High-Throughput QC-LDPC Decoder With TDMP Scheduling

Low-density parity-check (LDPC) codes with turbodecoding message-passing (TDMP) scheduling can obtain good performance and high convergence rates. In addition, the min- sum (MS) algorithm can reduce the complexity. The hybrid normalized MS algorithm with TDMP scheduling is presented to achieve good performance and to lower the complexity. For a quasi-cyclic LDPC (QC-LDPC) code with a long code length, parallel degree optimization and an offset iterative sequence rule are proposed. With the proposed techniques, the data correlation problem and memory access conflicts during TDMP scheduling can be resolved so that the iteration can smoothly proceed through the reasonable division of each block row. Fabricated in the 90-nm 1-Poly 9-Metal (1P9M) CMOS process, a multimode 96000-bit irregular QC-LDPC decoder is implemented. It attains throughputs of 1.7-3.0 Gb/s and dissipates an average power of 502 mW at an operation frequency of 100 MHz and at 10 iterations. The decoder chip area is 13.32 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , with a core area of 9.73 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

On the Overflow Problem in Finite Precision Turbo Decoding Message Passing

Much attention has been paid recently to the so-called layered decoding of LDPC codes, also known as turbo-decoding message passing (TDMP). The TDMP algorithm for decoding LDPC codes is known to possess some desirable features, such as fast convergence speed, reduced memory requirements and reduced implementation complexity in comparison with standard two-phase message passing algorithm. In this paper we analyze an important issue connected with hardware implementation of TDMP algorithm, namely the finite precision representation of messages influence on the decoding performance. Constrained dynamic range of the finite precision representation of messages entails overflow errors. We present an analysis revealing that in the subsequent decoding iterations, the subtraction of non-overflowed intrinsic message from overflowed extrinsic message is a source of errors that have substantial impact on the decoding results. The analysis is confirmed by simulation results showing significant performance loss. However this performance loss can be almost completely eliminated with a basic modifications in the messages computation algorithm. Effectiveness of the presented modifications is confirmed by simulation results obtained with hardware TDMP decoder implementation that has been developed.

Scheduling parity checks for increased throughput in early-termination, layered decoding of QC-LDPC codes on a stream processor

A stream processor is a power-efficient, high-level-language programmable option for embedded applications that are computation intensive and admit high levels of data parallelism. Many signal-processing algorithms for communications are well matched to stream-processor architectures, including partially parallel implementations of layered decoding algorithms such as the turbo-decoding message-passing (TDMP) algorithm. Communication among clusters of functional units in the stream processor impose a latency cost during both the message-passing phase and the parity-check phase of the TDMP algorithm with early termination; the inter-cluster communications latency is a significant factor in limiting the throughput of the decoder. We consider two modifications of the schedule for the TDMP algorithm with early termination; each halves the communication required between functional-unit clusters of the stream processor in each iteration. We show that these can provide a substantial increase in the information throughput of the decoder without increasing the probability of error.

An Area-Efficient Reconfigurable LDPC Decoder with Conflict Resolution

Based on Turbo-Decoding Message-Passing (TDMP) and Normalized Min-Sum (NMS) algorithm, an area efficient LDPC decoder that supports both structured and unstructured LDPC codes is proposed in this paper. We introduce a solution to solve the memory access conflict problem caused by TDMP algorithm. We also arrange the main timing schedule carefully to handle the operations of our solution while avoiding much additional hardware consumption. To reduce the memory bits needed, the extrinsic message storing strategy is also optimized. Besides the extrinsic message recover and the accumulate operation are merged together. To verify our architecture, a LDPC decoder that supports both China Multimedia Mobile Broadcasting (CMMB) and Digital Terrestrial/ Television Multimedia Broadcasting (DTMB) standards is developed using SMIC 0.13µm standard CMOS process. The core area is 4.75mm2 and the maximum operating clock frequency is 200MHz. The estimated power consumption is 48.4mW at 25MHz for CMMB and 130.9mW at 50MHz for DTMB with 5 iterations and 1.2V supply.

A Cost-Efficient LDPC Decoder for DVB-S2 with the Solution to Address Conflict Issue

In this paper, a cost-efficient LDPC decoder for DVB-S2 is presented. Based on the Normalized Min-Sum algorithm and the turbo-decoding message-passing (TDMP) algorithm, a dual line-scan scheduling is proposed to enable hardware reusing. Furthermore, we present the solution to the address conflict issue caused by the characteristic of the parity-check matrix defined by DVB-S2 LDPC codes. Based on SMIC 0.13µm standard CMOS process, the LDPC decoder has an area of 12.51mm2. The required operating frequency to meet the throughput requirement of 135Mbps with maximum iteration number of 30 is 105MHz. Compared with the latest published DVB-S2 LDPC decoder, the proposed decoder reduces area cost by 34%.

A Turbo-Decoding Message-Passing Algorithm for Sparse Parity-Check Matrix Codes

A turbo-decoding message-passing (TDMP) algorithm for sparse parity-check matrix (SPCM) codes such as low-density parity-check, repeat-accumulate, and turbo-like codes is presented. The main advantages of the proposed algorithm over the standard decoding algorithm are 1) its faster convergence speed by a factor of two in terms of decoding iterations, 2) improvement in coding gain by an order of magnitude at high signal-to-noise ratio (SNR), 3) reduced memory requirements, and 4) reduced decoder complexity. In addition, an efficient algorithm for message computation using simple “max” operations is also presented. Analysis using EXIT charts shows that the TDMP algorithm offers a better performance–complexity tradeoff when the number of decoding iterations is small, which is attractive for high-speed applications. A parallel version of the TDMP algorithm in conjunction with architecture-aware (AA) SPCM codes, which have embedded structure that enables efficient high-throughput decoder implementation, are presented. Design examples of AA-SPCM codes based on graphs with large girth demonstrate that AA-SPCM codes have very good error-correcting capability using the TDMP algorithm.

A 640-Mb/s 2048-Bit Programmable LDPC Decoder Chip

A 14.3-mm/sup 2/ code-programmable and code-rate tunable decoder chip for 2048-bit low-density parity-check (LDPC) codes is presented. The chip implements the turbo-decoding message-passing (TDMP) algorithm for architecture-aware (AA-)LDPC codes which has a faster convergence rate and hence a throughput advantage over the standard decoding algorithm. It employs a reduced complexity message computation mechanism free of lookup tables, and features a programmable network for message interleaving based on the code structure. The chip decodes any mix of 2048-bit rate-1/2 (3,6)-regular AA-LDPC codes in standard mode by programming the network, and attains a throughput of 640 Mb/s at 125 MHz for 10 TDMP-decoding iterations. In augmented mode, the code rate can be tuned up to 14/16 in steps of 1/16 by augmenting the code. The chip is fabricated in 0.18-/spl mu/m six-metal-layer CMOS technology, operates at a peak clock frequency of 125 MHz at 1.8 V (nominal), and dissipates an average power of 787 mW.