Tunnel Junction Memory Research Articles

Enhanced the performance of lead-free material-based magnetoresistance random access memory

The field of Spintronics uses a spin-dependent current to control the electron spin. Magnetic tunnel junctions (MTJs) are essential in spintronics because of their wide range of applications, especially their great scaling ability, fast write speeds, and high relative magnetoresistances. The performance of MTJ devices based on a single MgO barrier is poor compared to a double barrier layer. The lead free double perovskite materials can be used to enhance the performance and stability of MTJ. In this paper, perovskite materials (Cs2CuBiCl6, Cs2CuBiF6, and Cs2CuBiI6) are added to the MgO dielectric layer to form a Penta layer MTJ. The MTJ device performance parameters, such as tunneling magnetoresistance (TMR), differential resistance, antiparallel and parallel resistance, and differential TMR, with these materials as composite dielectrics, have been investigated using the non-equilibrium Green’s function (NEGF) simulator. The TMR (%) of Fe-MgO- Cs2CuBiF6 - Fe-MgO-based MTJ devices at room temperature is 1307%. The implementation of the magnetoresistance random access memory based on the suggested MTJ model has been demonstrated using the LTspice. The power dissipation of the Fe-MgO- Cs2CuBiF6- MgO-Fe-based MTJ model is low as compared to the other two double perovskite-based MTJ models. Hence, MTJ memory devices with composite dielectrics based on Cs2CuBiF6 perform better.

Monolithic three-dimensional hafnia-based artificial nerve system

Artificial nerve systems that mimic the tactile perception ability of human skin could be adopted in the realization of devices for a hyperconnected society, including prosthetic devices, interfaces for virtual reality, and smart sensors. The system consists of a pressure sensor, memory, and signal processing circuit, which possess the capability of generating sensory neuron-like signals. Although technological advances have been made in semiconductor-based memory and transistors over the decades, sensor technology is still relying on micro-electromechanical systems, which are hard to realize miniaturization/high-density and high-performance technology. Here, we demonstrate a monolithic three-dimensional integrated artificial nerve on the basis of ferroelectric HfxZr1-xO2 for use in the core element of neuromorphic memory and a self-powered piezoelectric pressure sensor. The morphotropic phase boundary (MPB) state of hafnia film was formed between orthorhombic and tetragonal phases for high piezoelectric performance. The MPB-based sensor was integrated with self-rectifying ferroelectric tunnel junction memory and silicon-based ring oscillator. We realized a frequency-modulated pulse-like synaptic signal with pressure detection ability over a wide range of 1–50 kPa and a good sensitivity of 0.35 mV/kPa. Also, we demonstrate the real-time frequency-modulated operation of the artificial nerve system by adjusting the functional properties of the hafnia films.

Impact of annealing temperature on the remanent polarization and tunneling electro-resistance of ferroelectric Al-doped HfOx tunnel junction memory.

The ferroelectric characteristics of a metal-ferroelectric-metal (MFM) ferroelectric tunneling junction (FTJ) capacitor device are investigated herein. The device consists of an aluminum-doped hafnium oxide (HAO) insulator sandwiched between tungsten (W) and titanium nitride (TiN) metal electrodes. Rapid thermal annealing (RTA) is performed for 20 s under a nitrogen atmosphere at temperatures of 750 °C, 800 °C, and 850 °C to find that ferroelectricity with a large remanent polarization (Pr) of 41.28 μC cm-2 can be obtained at the optimum annealing temperature of 800 °C. The presence of ferroelectricity is confirmed by polarization-switching positive-up-negative-down (PUND) measurements and by the hysteric polarization-voltage (P-V) loop. All devices exhibit excellent reliability, with an endurance of up to ∼106 cycles and long retention characteristics. In addition, the interfacial paraelectric capacitance (Ci) values of the three HAO FTJs are investigated via pulse-switching measurements. The results indicate that the HAO film annealed at 800 °C for 20 s exhibits an excellent tunneling electro-resistance (TER) ratio of 186% and this is attributed to the extra paraelectric layer formed between the ferroelectric layer and the bottom electrode. The detailed findings of this study are expected to assist in the development of hafnium oxide-based ferroelectric non-volatile memory applications.

Thermally Robust Perpendicular SOT-MTJ Memory Cells With STT-Assisted Field-Free Switching

A back-end-of-line compatible 400 °C thermally robust perpendicular spin-orbit torque magnetic tunnel junction (p-SOT-MTJ) memory cell with a tunnel magnetoresistance ratio of 130% is demonstrated. It features an energy-efficient spin-transfer-torque-assisted field-free spin-orbit torque (SOT) switching and a novel interface-enhanced synthetic antiferromagnet (SAF). The optimal SAF with a Ru (9 Å) spacer sandwiched by Co/Pt multilayers has a high SAF coupling field of 2.8 kOe. The parallel magnetic coupling between the CoFeB-based reference layer and the bottom Co/Pt multilayer is enhanced by a magnet-coupling face-centered cubic textured Co/Pt (5 Å) multilayer buffer. The thermally induced Pt–Fe interdiffusion is effectively reduced by the W (3 Å) trilayers of texture-decoupling diffusion multibarrier. The Ta/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula> -W and TaN/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula> -W composite SOT channels are thick enough to be the etching stop and sustain 400 °C annealing without transforming to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\alpha $ </tex-math></inline-formula> -W. Using the harmonic Hall voltage measurement, the Ta/W and TaN/W channels exhibit the large effective spin Hall angle of approximately −0.21 and −0.27, respectively. Scaling magnetic tunnel junction (MTJ) down to 30 nm size can reduce the switching time due to single-domain switching based on the micromagnetic simulation. The damping constant of ~0.018 is obtained by the ferromagnetic resonance measurement. A bigger damping constant reduces the switching time as predicted by the calibrated simulation.

Domain wall-magnetic tunnel junction spin–orbit torque devices and circuits for in-memory computing

There are pressing problems with traditional computing, especially for accomplishing data-intensive and real-time tasks, that motivate the development of in-memory computing devices to both store information and perform computation. Magnetic tunnel junction memory elements can be used for computation by manipulating a domain wall, a transition region between magnetic domains, but the experimental study of such devices has been limited by high current densities and low tunnel magnetoresistance. Here, we study prototypes of three-terminal domain wall-magnetic tunnel junction in-memory computing devices that can address data processing bottlenecks and resolve these challenges by using perpendicular magnetic anisotropy, spin–orbit torque switching, and an optimized lithography process to produce average device tunnel magnetoresistance TMR = 171% and average resistance-area product RA = 29 Ω μm2, close to the RA of the unpatterned film. Device initialization variation in switching voltage is shown to be curtailed to 7%–10% by controlling the domain wall initial position, which we show corresponds to 90%–96% accuracy in a domain wall-magnetic tunnel junction full adder simulation. Repeatability of writing and resetting the device is shown. A circuit shows an inverter operation between two devices, showing that a voltage window is large enough, compared to the variation noise, to repeatably operate a domain wall-magnetic tunnel junction circuit. These results make strides in using magnetic tunnel junctions and domain walls for in-memory and neuromorphic computing applications.

Effects of Process-Induced Defects on Polarization Switching in Ferroelectric Tunneling Junction Memory

The scaling effects of ferroelectric tunnel junction (FTJ) memory are investigated by evaluating remanent polarization ( ${P} _{\mathrm {r}}$ ), coercive field ( ${E} _{\mathrm {c}}$ ), and polarization switching speed. Through the analysis on dc tunneling currents and frequency responses of ${E} _{\mathrm {c}}$ and ${P} _{\mathrm {r}}$ for FTJs with various sizes, it is found that polarization switching mechanism (domain nucleation limit) is not changed by the width reduction. However, by the length scaling, domain wall spreading-limited switching becomes dominant by process-induced damaged edge regions, leading to the larger ${P}_{\mathrm {r}}$ and the faster switching speed.

(Invited) Ferroelectric-HfO2 Devices: Physics and Applications

1. Introduction Ferroelectric-HfO2 (FE-HfO2) is a key technology enabler for energy-efficient memory devices because of its high scalability and CMOS-compatibility [1]. FE memory device is low-power, high-speed and high reliability by field-driven operation. FE memory device can be implemented in the form of capacitor, resistor, and transistor, which provides us design flexibility of memory system. Thanks to the material break-through and the device architecture innovation, FE memory device opens up new opportunities in memory market. In this talk, I will overview our recent research progress on FE-HfO2 memory devices and discuss future perspectives. 2. Capacitor memory - NVSRAM The most mature device structure is capacitor type. It is natural to replace conventional FE-material by scalable FE-HfO2. We can take an advantage of low power operation of FE-HfO2 for smart power management in IoT application. IoT sensor node devices are expected to operate in an intermittent mode. The active rate of a transistor is much lower than clock frequency in IoT device. In order to suppress standby leakage power, especially in SRAM, it is important to bring the transistors in sleep mode as much as possible. Normally-off computing is the idea that stores the current state data in NV memory, turns the power off, and restore the data after power-on without much latency and power overhead. NV-SRAM [2] has been revisited by using FE-HfO2 which realizes good scalability as well as cost effective process. NV-SRAM has been designed, fabricated by integrating FE-HfO2 capacitor [3] in back-end process as shown in Fig. 1. Store, power-off, and recall operation are successfully demonstrated. 3. Resistive memory - FTJ Ferroelectric Tunnel Junction (FTJ) memory is an emerging memory for high capacity memory. A ferroelectric thin film is sandwiched by two electrodes, which works as resistive change memory, as shown in Fig. 2. FTJ was proposed back in 1970s [4] and current state-of-the-art nanoscale ferroelectric thin film technologies are to finally realize it. FTJ utilizes polarization switching to change on-sate and off-state tunneling electroresistance (TER). Design guideline and high TER as much as >30 has been recently demonstrated by FE-HfO2 (Fig. 2) [5]. FTJ also shows multi-level cell operation and high resistance, which are useful for hardware AI application. Moreover, scalability has been thoroughly investigated by self-consistent potential and non-equilibrium Green function method to compete with other high capacity memories (Fig. 3) [6]. 4. Transistor memory - FeFET Ferroelectric FET (FeFET) memory is a transistor which has a thin FE layer as gate insulator. This is another type of device structure for high capacity memory. Recently, 3D stacked FeFET has been proposed [7], which can possibly compete with NAND flash memory in terms of memory capacity.There are several challenges to realize such 3D stacked FeFET using conventional poly-Si channel. Poly-Si channel has low mobility and forms a low-k interfacial layer which causes voltage loss and reliability degradation by charge trapping. In this work, we propose to use amorphous oxide semiconductor, IGZO [8], as an alternative channel material. IGZO channel provides high mobility as a deposited channel and prevent low-k interfacial layer formation. We have demonstrated ferro- electricity in the combination of FE-HfO2 and IGZO (Fig. 4), and large memory window with nearly ideal subthreshold swing and high endurance operations [9]. 5. Conclusions FE-HfO2 is a key technology enabler for energy-efficient computing because of its high scalability and CMOS-compatibility. NVSRAM serves for smart power management in IoT applications. FTJ and FeFET have a potential for low power and high capacity memory as well as machine learning accelerator. Acknowledgment The author acknowledges Nozomu Ueyama, Yusaku Tagawa, Fei Mo, Kiyoshi Takeuchi, Takuya Saraya and Toshiro Hiramoto for technical discussion and help. This work is partly supported by JST CREST 16815651, JST PRESTO 15656058, MEXT KAKENHI 16K18085 and 18H01489.

Short-Term Long-Term Compute-in-Memory Architecture: A Hybrid Spin/CMOS Approach Supporting Intrinsic Consolidation

Biological memory structures impart enormous retention capacity while automatically providing vital functions for chronological information management and update the resolution of the domain and episodic knowledge. A crucial requirement for hardware realization of such cortical operations found in biology is to first design both short-term memory (STM) and long-term memory (LTM). Herein, these memory features are realized via a beyond-CMOS-based learning approach derived from the repeated input information and retrieval of the encoded data. We first propose a new binary STM-LTM architecture with composite synapse of the spin Hall effect-driven magnetic tunnel junction (SHE-MTJ) and capacitive memory bit cell to mimic the behavior of biological synapses. This STM-LTM platform realizes the memory potentiation through a continual update process using STM-to-LTM transfer, which is applied to neural networks based on the established capacitive crossbar. We then propose a hardware-enabled and customized STM-LTM transition algorithm for the platform considering the real hardware parameters. We validate the functionality of the design using SPICE simulations that show the proposed synapse has the potential of reaching ~30.2-pJ energy consumption for STM-to-LTM transfer and 65 pJ during STM programming. We further analyze the correlation between energy, array size, and STM-to-LTM threshold utilizing the MNIST data set.

Low-Current-Density Magnetic Tunnel Junctions for STT-RAM Application Using MgO$_{{x}}$ N$_{\text{1}-{x}}\,\,({x}=\text{0.57}$ ) Tunnel Barrier

High switching speed, endurance, and low-current-based perpendicular magnetic tunnel junction (p-MTJ) memory is attracting wide interest as a key promising candidate for next-generation spintronic memory technology. p-MTJ-based spin-transfer torque RAM (STT-RAM) has been extensively investigated, and despite the promise, there is concern about the high switching current density and low stability with regard to scaling. In this work, the current controllability of p-MTJ in iron (Fe)-enriched Co20Fe60B20 with a newly designed MgO x N1– x tunnel layer is systematically investigated, with the expectation that the introduction of N minimizes the oxidation of Fe to improve the performance of the device. A facile, plasma-based oxynitridation (MgO x = 0.57N1– x =0.43) of MgO through RF-sputter deposition serves as a reliable procedure to establish a tunnel barrier for an MTJ structure fabricated with ~300-nm diameter and pinned with synthetic antiferromagnetic (SAF) [Co/Pt] ${_{n}}$ multilayer stack. Current-controlled tunneling magnetoresistance (TMR) up to ~65% was observed at room temperature (RT) with ultralow switching current density ( ${J}_{c}$ ) of 136 ± 17 kA/cm2. TMR along with tunnel conductance ( ${g}$ ( ${V}$ )) was measured to be highly stable in the read-bias regime (−200 to +200 mV) for MgO x N1– x as compared to the reported MgO barrier. The analogous MgO x N1– x -based MTJ structures were modeled using the nonequilibrium Green’s function (NEGF) with appropriate tunnel barrier parameters and incorporating modulated barrier height as compared with the MgO barrier. The current–voltage characteristics of the modeled device showed close agreement with experimental data indicating high spin current. Based on the field-induced magnetization analysis, the macro-magnetic reversal analysis suggests the free-layer switching duration of ~3 ns. These observations show the strong candidature of MgO x N1– x ( ${x} = {0.57}$ ) MTJs for STT-RAM device application.

Understanding tunneling electroresistance effect through potential profile in Pt/Hf0.5Zr0.5O2/TiN ferroelectric tunnel junction memory

Hafnia ferroelectric materials have gained prominence as promising materials for advanced memory applications due to their high scalability and full-complementary metal oxide semiconductor compatibility. In this paper, we present a comprehensive study on the electrical properties of Pt/Hf0.5Zr0.5O2/TiN asymmetric ferroelectric tunnel junction (FTJ) devices. The ferroelectric behavior of 4- and 5-nm Hf0.5Zr0.5O2 (HZO) thin films was confirmed by using piezoresponse force microscopy and conductive-atomic force microscopy. The typical current–voltage characteristics of the FTJ devices with two resistance states due to the tunneling electroresistance (TER) effect have been analyzed using a direct tunneling model based on the Wentzel-Kramers-Brillouin approximation. Further, we have proposed a method to extract the effective mass of the HZO thin film by numerical analysis using the MOS leakage current model. Finally, a dependence of the TER on the HZO thickness is analyzed to realize a high TER ratio.

Characterization and Modeling of Co/BaTiO3/SrRuO3 Ferroelectric Tunnel Junction Memory by Capacitance–Voltage (${C}$ –${V}$ ), Current–Voltage (${I}$ –${V}$ ), and High- Frequency Measurements

Ferroelectric tunnel junction (FTJ) is a promising low power nonvolatile memory for beyond-CMOS applications. In this paper, Co/BaTiO3/SrRuO3 FTJs are fabricated, simulated, and their electrical characteristics are measured by capacitance–voltage ( ${C}$ – ${V}$ ), current–voltage ( ${I}$ – ${V}$ ), and high-frequency S-parameter measurements. Ferroelectricity of the ultrathin BaTiO3 (~3.2 nm) film is first verified by a butterfly shaped hysteresis ${C}$ – ${V}$ profile, from which saturation polarizations are calculated in the ON state and OFF state as ${P}_{ \mathrm{ON}}=+ {20}\,\,\mu {C} / {\text{cm}}^{ {2}}$ and ${P}_{ \mathrm{OFF}}=- {25}\,\,\mu {C}/{\text{cm}}^{ {2}}$ , respectively. The numerical simulation of the FTJ device is performed using experimental electronic band parameters of the heterostructure. The device structure was optimized for ON/OFF ratio, ${I}_{ \mathrm{ON}} / {I}_{ \mathrm{OFF}}= {75}$ for a depolarization field, ${E}_{{dpol}} . The calculated tunnel currents of $ {250}\,\,{nm}\times {250}\,\,{nm}$ FTJ in ON state ( ${I}_{ \mathrm{ON}}= {250}\times {250}^{- {250}}\,\,{A}$ ) and OFF state ( ${I}_{{OFF}}={{1.75}\times {250}}^{{-9}}\,\,{A}$ ) match with experimental values. From the S-parameters of RF measurements, the high-frequency small-signal device model of the FTJ in ON state ( ${C}_{ \mathrm{ON}}= {250}\,\,{fF},{R}_{ \mathrm{ON}}={0.8}\,\,{M}\Omega$ ) and OFF state ( ${C}_{ \mathrm{OFF}}={ {250}}\,\,{fF},{R}_{ \mathrm{OFF}}= {250}\,\,{M}\Omega$ ) is developed for a frequency range from 50 MHz to 5 GHz. The extracted capacitor model of Co/BaTiO3/SrRuO3 FTJ is useful for high-frequency simulation of benchmark FTJ circuits.

Tetragonal Mn3Sn Heusler films with large perpendicular magnetic anisotropy deposited on metallic MnN underlayers using amorphous substrates

Tetragonal Heusler compounds that exhibit large perpendicular magnetic anisotropy are promising materials for advanced spintronic devices. A prerequisite are thin films whose tetragonal axis is oriented perpendicular to the plane of the films. Here we show that highly textured, (001) oriented, tetragonal Mn3Sn layers can be prepared using metallic zinc-blende (ZB) MnN as underlayers. Moreover, we show that these layers can be deposited on amorphous substrates using reactive magnetron sputtering. The ferrimagnetic Mn3Sn layers exhibit perpendicularly magnetized hysteresis loops with coercive fields of ∼2 T. Stoichiometric ZB-MnN underlayers share an “equivalent” Mn-Mn layer at the interface with Mn3Sn, thus promoting their oriented growth. Other nitride underlayers are not effective due to their rock-salt (RS) crystal structure and the absence of Mn. Density functional theory calculations confirm that tetragonal Mn3Sn Heusler films are energetically stable when interfaced with ZB-MnN underlayers and not with any of the other RS nitride underlayers considered here. Such Heusler compounds have much promise as electrodes for magnetic tunnel junction memory elements for deeply scaled magnetic random access memories.

Ferroelectric HfO2 Tunnel Junction Memory With High TER and Multi-Level Operation Featuring Metal Replacement Process

We have investigated device design of HfO2-based ferroelectric tunnel junction (FTJ) memory. Asymmetry of dielectric screening property in top and bottom electrodes is the key for high tunneling electroresistance (TER) ratio. Thus, metal and semiconductor electrodes are proposed. There exists a design space of ferroelectric material parameters to achieve high TER ratio under the constraint of depolarizing field. We have developed an FTJ fabrication process to realize the design. Large polarization charge and symmetric switching voltage are obtained by top metal replacement process. High TER ratio >30 and multi-level cell operation have been successfully demonstrated. Retention characteristics is promising, however, endurance characteristics should be improved for reliable operation.

(Invited) Technology Breakthrough by Ferroelectric HfO2 for Low Power Logic and Memory Applications

In today’s highly information-oriented society, more and more electronic devices are needed for high-end servers in cloud and sensor node devices in edge. Because of the power constraint, highly energy-efficient computing is required, which new transistor and memory technologies enable [1]. As a general guideline for energy-efficient computing, higher Ion/Ioff at lower supply voltage is obtained by using steep subthreshold slope (SS) transistor, and normally-off operation is performed without much overhead by using non-volatile memory. Those logic and memory technologies must be developed at low cost. Recent discovery of ferroelectric (FE) HfO2 [2] will realize low-cost and energy-efficient logic and memory devices. In this paper, the recent status of negative capacitance FET (NCFET), non-volatile SRAM (NV-SRAM), and FE tunnel junction memory (FTJ), all of which are based on FE-HfO2, will be overviewed. NCFET is the transistor which has ferroelectric gate insulator and uses negative capacitance to amplify surface potential. It has been regarded as one of the most promising steep SS transistors because of (1) high Ion/Ioff ratio with high Ion, (2) CMOS process compatibility, and (3) minimum circuit modification, with the use of FE-HfO2 at low cost. Device design guideline revealed that NCFET can operate at as low as 0.2V supply voltage [3]. Moreover, NCFET gate stack material can fit to advanced CMOS process with replacement gate FinFET [4] and Nanowire [5]. In recent years, there were encouraging experimental demonstrations of steep SS in long and short channel devices. Operation speed of NCFET may be limited by the dynamics of atomic displacement and domain dynamics [3,6], which is one of the central topics. NC effect is regarded as an additive performance booster and expected to synthesize with novel channel material and other steep SS transistors such as TFET [7]. IoT sensor node devices are expected to operate in an intermittent mode. The active rate of a transistor is much lower than clock frequency in IoT device. In order to suppress standby leakage power, especially in SRAM, it is important to bring the transistors in sleep mode as much as possible [1]. Normally-off computing is the idea that stores the current state data in NV memory and restore the data after wake-up without much latency and power overhead. NV-SRAM has been revisited by using FE-HfO2 which realizes good scalability as well as cost effective process [8]. NV-SRAM has been recently designed, fabricated by integrating FE-HfO2 capacitor in back-end process, and characterized. Store, power-off, and recall operation are successfully demonstrated. New AI algorithms such as deep learning have made big impacts in business, however, it requires enormous amount of computing power. In order to use such algorithm in edge devices, energy efficiency should be greatly improved and hardware implementation of such algorithm will be highly required. Recently, artificial neural network (ANN) has been realized by using synaptic device such as resistive change RAM (ReRAM) as nonvolatile analog memory. FE memory is also the alternative for synaptic device. FTJ is an emerging memory cell which utilizes polarization switching to change on-sate and off-state tunneling electroresistance (TER) . FTJ has been recently demonstrated by using FE-HfO2 with as high TER as >30 and multi-level cell operation [9]. Linearity and reliability should be further examined for ANN applications.

Enhanced Non-Linearity Factor in Ferroelectric Tunnel Junction Based on HfO2 Heterojunction

Ferroelectric polarization, related to charge conduction, has shown some intriguing properties in ferroelectric tunnel junction as it has higher on/off ratio, lower power consumption and shorter process time. Conventional ferroelectrics have various problems when it is based on perovskite structure material, such as poor Si-compatibility, lead pollution and small energy bandgap. Recently, both ferroelectricity and anti-ferroelectricity have been reported in doped HfO2 thin film (<30 nm). The ferroelectricity and anti-ferroelectricity HfO2 thin films can be extremely thin with good Si-compatibility and large bandgap (>5 eV). Anti-ferroelectric/ferroelectric HfO2 heterojunction can enhance fatigue property and non-linearity of single ferroelectric tunnel junction. The space charge can be induced due to the stress in ferroelectric layer or ferroelectric/metal interface in 90° domain switching while anti-ferroelectric lowers the stress in the 180° domain switching. The HfO2 heterojunction can have non-linearity as it has higher resistance state under the threshold voltage for polarization switching. This structure with good fatigue property and non-linearity factor would contribute to the enhancement of ferroelectric tunnel junction memory device. This research was supported by the MOTIE (Ministry of Trade, Industry & Energy (#10080643) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device.

Ab initio study of mono-layer 2-D insulators (X-(OH)2 and h-BN) and their use in MTJ memory device

The paper presents an ab initio study of the 2-D insulators and their effect on the performance of a magnetic tunnel junction memory (MTJ) device. MTJ devices has been considered as an alternate to the charge based data storage cells due to its spin-polarised operation and high scaling probability. The use of 2-D insulators like X-(OH)2 (X: Ca and Mg) and h-BN (hexagonal-Boron Nitride) in such device would be interesting. The authors have calculated the band structures, density of states and effective mass of electrons and holes for the mono-layer of these three non-conventional 2-D insulators using the first principle calculations in density functional theory framework using Quantumwise ATK tool. The ab initio calculation yielded band gap (Eg) of 4.633, 4.685 and 4.249 eV for h-BN, Ca(OH)2 and Mg(OH)2, respectively. The effective mass of electrons was calculated as 0.621, 0.604 and 0.478 for single layer h-BN, Ca(OH)2 and Mg(OH)2, respectively. While for holes it is 0.834, 0.446 and 0.407, respectively for h-BN, Ca(OH)2 and Mg(OH)2. The MTJ device properties as tunneling-magneto resistance, differential TMR, parallel and anti-parallel resistance, differential resistance and spin transfer torque components (in-plane and out-of-plane) with these materials as composite dielectric has been reported in this paper using MTJ Lab tool. The performance of MTJ memory device with h-BN based composite dielectric is found better.

High reliability sensing circuit for deep submicron spin transfer torque magnetic random access memory

A high reliability offset-tolerant sensing circuit is presented for deep submicron spin transfer torque magnetic tunnel junction (STT-MTJ) memory. This circuit, using a triple-stage sensing operation, is able to tolerate the increased process variations as technology scales down to the deep submicron nodes, thus improving significantly the sensing margin. Meanwhile, it clamps the bit-line voltage to a predefined small bias voltage to avoid any read disturbance during the sensing operations. By using the STMicroelectronics CMOS 40 nm design kit and a precise STT-MTJ compact model, Monte Carlo simulations have been carried out to evaluate its sensing performance.

Ferroelectric Tunnel Junction Memory Devices made from Monolayers of Vinylidene Fluoride Oligomers

Conductance bistability in Pt/Si–vinylidene fluoride (VDF) oligomer–Au ferroelectric tunnel junction devices is demonstrated. I–V and C–V measurements reveal bistable conductance switching within biasing voltage of ±0.5V with stable memory retention up to 1 × 104 cycles. The memory element exhibits a low switching voltage of ±1.0 V, coincides with the coercive field of the ferroelectric VDF oligomer monolayer films in use.

A High-Reliability, Low-Power Magnetic Full Adder

Recently, ultra-low power circuits based on logic-in magnetic tunnel junction (MTJ) memory structure have been studied thanks to its non-volatility, infinite endurance, high access speed, and easy integration with CMOS process. However, this type of circuit suffers from low reliability both in memory cell and sensing amplifier circuits, which greatly limits its practical applications for logic computation. In this paper, we present a new design of magnetic full adder (MFA) to overcome this issue based on the thermally assisted switching (TAS) MTJ cell and pre-charge sensing amplifier (PCSA) circuit. By using CMOS 65 nm design kit and a precise TAS-MTJ model, mixed simulations have been performed to demonstrate its high reliability keeping low power and small die area.

Effect of resistance-area product on spin-transfer switching in MgO-based magnetic tunnel junction memory cells

We use ultrafast current-induced switching measurements to study spin-transfer switching performance metrics, such as write energy per bit (EW) and switching current density (Jc), as a function of resistance-area product (RA) (hence MgO thickness) in magnetic tunnel junction cells used for magnetoresistive random access memory (MRAM). EW increases with RA, while Jc decreases with increasing RA for both switching directions. The results are discussed in terms of RA optimization for low write energy and current drive capability (hence density) of the MRAM cells. Switching times &amp;lt;2 ns and write energies &amp;lt;0.3 pJ are demonstrated for 135 nm×65 nm CoFeB/MgO/CoFeB devices.