True Random Number Generator Circuit Research Articles

Controllable Electrical Properties of ZrO2/BiFeO3 Bilayer Memristor from Synaptic Mimic to TRNG Circuit Application by Modulating Compliance Currents

AbstractApart from simulating biological synapses, memristors can also be used in the secure encryption by exploiting their inherent random resistive switching (RS) properties. In this work, nonvolatile Ta/BiFeO3/ZrO2/Pt memristor is fabricated with 2 nm inserting BiFeO3 layer. At a high compliance current of 10 mA, it presents gradual RS characteristics during the set process, which resulting in 30 conductance states. Synaptic behavior can be successfully mimicked by precise conductance modulating under pulse electrical stimulation. Whereas under a low compliance current of 500 µA, it exhibits abrupt RS behavior, and the set voltage ranged from 0.3–0.8 V, which can be effectively as an entropy source for true random number generator (TRNG). Due to its Shannon entropy of 300 bits is 0.99987, Hamming weights and intra‐Hamming distances tend to be 50%. Furthermore, the software simulation of encryption and decryption of cat image is achieved by combining the key generated by TRNG. The controllable electrical properties of the Ta/BiFeO3/ZrO2/Pt device can be modulated by the compliance current, thus meeting the computing or safety requirements, which provides a solid foundation for the development of integrating computation and security at the hardware level.

Voltage and temperature dependence of Random Telegraph Noise and their impacts on random number generator

With the continuous decrease in device dimensions, Random Telegraph Noise (RTN) has drawn increasing attention. From the intrinsic stochastic features, RTN signal is adopted as an entropy source for true random number generator (TRNG). In this study, RTN time constants are investigated under various gate voltages and temperatures. Their impacts on the TRNG are revealed by performing the National Institute of Standards and Technology (NIST) test. It is found that the random verification is highly dependent on the maximum frequency (fmax) of the clock signal in TRNG circuit, which shows linear dependence with the RTN time constant (τc + τe). Our findings may make a step towards generating truly random numbers and improving hardware or cyber security based on RTN phenomenon.

Compact Programmable True Random Number Generator Based on Spin Torque Nano-Oscillator

True Random Number Generator(TRNG) is the key component for stochastic computation. It can also act as the Probabilistic Bit(P-Bit) which is the core device for Ising Computer. In previous study, we have proposed a novel programmable TRNG based on Spin Torque Nano-Oscillator(STNO). With this TRNG constructed with STNO, a time division multiplexing Ising computer is designed to work under the Incremental Coupling Rule. However, the programmable TRNG is still lack of a corporeal hardware implementation. In this work, a SPICE model for STNO which can accurately describe the frequency, resistance as well as noise spectrum is provided first. And then, a compact optimized Schmitt trigger circuit with 14 nm FinFET technology is proposed to construct the programmable TRNG. Finally, the performance of the compact programmable TRNG circuit is evaluated and discussed.

A rate-adjustable true random number generator based on the stochastic delay of a TiN/NbOx/Pt memristor

True random number generator (TRNG) is a critical component in hardware security that is increasingly important in the era of mobile computing and internet of things. A memristor is a promising candidate to construct a TRNG due to its intrinsic variability of switching behavior and high-density integration. Here, we present a 1T1R oscillation structure with a TiN/NbOx/Pt memristor for constructing a rate-adjustable TRNG. The randomness of the oscillation comes from the stochastic switch latency of the memristor. The experimental results demonstrate that the oscillation rate can be modulated by changing the gate bias of the transistor in series. Furthermore, a TRNG circuit with adjustable rates is constructed based on the 1T1R oscillation, and the simulated results revealed that the proposed TRNG output can pass eight NIST tests, indicating the true randomness of the circuit. Finally, the randomness in the memristor, the adjustable rate of the 1T1R oscillation, and the NIST test result of RNG are proved in turn. These results demonstrate the feasibility of the circuit, which can minimize the power consumption by adjusting the random number generation rate to correct the frequency drift caused by extrinsic factors, such as environment temperature and humidity.

Data Encryption: Advanced Data Encryption ​using 2D Materials (Adv. Mater. 27/2021)

In article 2100185, Mario Lanza and co-workers use 2D multilayer hexagonal boron nitride (h-BN) to fabricate devices that exhibit stable random telegraph noise current signals, and employ them in true random number generator circuits for advanced data encryption. The currents are very stable because they are confined across the few-atoms-wide defects embedded within the crystalline and highly stable h-BN structure, which avoids their lateral propagation.

Demonstration of Three True Random Number Generator Circuits Using Memristor Created Entropy and Commercial Off-the-Shelf Components.

In this work, we build and test three memristor-based true random number generator (TRNG) circuits: two previously presented in the literature and one which is our own design. The functionality of each circuit is assessed using the National Institute of Standards and Technology (NIST) Statistical Test Suite (STS). The TRNG circuits were built using commercially available off-the-shelf parts, including the memristor. The results of this work confirm the usefulness of memristors for successful implementation of TRNG circuits, as well as the ease with which a TRNG can be built using simple circuit designs and off-the-shelf breadboard circuit components.

A Compact Low-Voltage True Random Number Generator Based on Inkjet Printing Technology

Printed electronics (PE) is a fast-growing field with promising applications in wearables, smart sensors, and smart cards, since it provides mechanical flexibility, and low-cost, on-demand, and customizable fabrication. To secure the operation of these applications, true random number generators (TRNGs) are required to generate unpredictable bits for cryptographic functions and padding. However, since the additive fabrication process of the PE circuits results in high intrinsic variations due to the random dispersion of the printed inks on the substrate, constructing a printed TRNG is challenging. In this article, we exploit the additive customizable fabrication feature of inkjet printing to design a TRNG based on electrolyte-gated field-effect transistors (EGFETs). We also propose a printed resistor tuning flow for the TRNG circuit to mitigate the overall process variation of the TRNG so that the generated bits are mostly based on the random noise in the circuit, providing a true random behavior. The simulation results show that the overall process variation of the TRNGs is mitigated by 110 times, and the generated bitstream of the tuned TRNGs passes the National Institute of Standards and Technology - Statistical Test Suite. For the proof of concept, the proposed TRNG circuit was fabricated and tuned. The characterization results of the tuned TRNGs prove that the TRNGs generate random bitstreams at the supply voltage of down to 0.5 V. Hence, the proposed TRNG design is suitable to secure low-power applications in this domain.

True Random Number Generator Integration in a Resistive RAM Memory Array Using Input Current Limitation

A novel True Random Number Generator circuit fabricated in a 130 nm HfO2-based resistive RAM process is presented. The generation of the random bit stream is based on a specific programming sequence applied to a dedicated memory array. In the proposed programming scheme, all the cells of the memory array are addressed at the same time while the current provided to the circuit is limited to program only a subset of the memory array, resulting in a stochastic distribution of cell resistance values. Some cells are switched in a low resistive state, other cells are slightly programmed to reach an intermediate resistance state, while the remaining cells maintain their initial high resistance state. Resistance values are next converted into a bit stream and confronted to National Institute of Standards and Technology (NIST) test benchmarks. The generated random bit stream has successfully passed twelve NIST tests out of fifteen. Compared to state-of-the-art resistive RAM-based true random number generators, our proposed methodology is the first one to leverage on programming current limitation at a memory array level.

A Low-Cost Highly Reliable Spintronic True Random Number Generator Circuit for Secure Cryptography

Generation of random numbers is one of the most important steps in cryptographic algorithms. High endurance, high performance and low energy consumption are the attractive features offered by the Magnetic Tunnel Junction (MTJ) devices. Therefore, they have been considered as one of the promising candidates for next-generation digital integrated circuits. In this paper, a new circuit design for true random number generation using MTJs is proposed. Our proposed circuit offers a high speed, low power and a truly random number generation. In our design, we employed two MTJs that are configured in special states. Generated random bit at the output of the proposed circuit is returned to the write circuit to be written in the relevant cell for the next random generation. In a random bitstream, all bits must have the same chance of being “0”or “1”. We have proposed a new XOR-based method in this paper to resolve this issue in multiple random generators that produce truly random numbers with a different number of ones and zeros in the output stream. The simulation results using a 45[Formula: see text]nm CMOS technology with a special model of MTJ validated the advantages offered by the proposed circuit.

Tunnel FET ambipolarity‐based energy efficient and robust true random number generator against reverse engineering attacks

This study presents a true random number generator (TRNG) harvesting random bits from delay variations of ambipolarity-based ring oscillator, designed using 20 nm InAs Tunnel FET (TFET). Exploiting the TFET transmission gate (TG) functional failure, TFET ambipolarity-based ring oscillator design has been proposed. Random variations are observed in the oscillating frequency of proposed ring oscillator by changing the TFET device ambipolarity. Exploring the same, a TFET ambipolarity-based TRNG circuit has been demonstrated. XOR gate-based post-processing unit is designed to further enhance the unpredictability and randomness of the output bits. The proposed TRNG has passed various NIST tests performed at a supply voltage of 0.5 V. In 20 nm, the proposed TFET TRNG has an area as low as 90 pm 2 and consumes 5.4 pJ/bit at 0.5 V supply voltage. Ambipolarity-based circuit design makes the proposed TRNG robust against reverse engineering attacks.

High-speed true random number generation based on paired memristors for security electronics

True random number generator (TRNG) is a critical component in hardware security that is increasingly important in the era of mobile computing and internet of things. Here we demonstrate a TRNG using intrinsic variation of memristors as a natural source of entropy that is otherwise undesirable in most applications. The random bits were produced by cyclically switching a pair of tantalum oxide based memristors and comparing their resistance values in the off state, taking advantage of the more pronounced resistance variation compared with that in the on state. Using an alternating read scheme in the designed TRNG circuit, the unbiasedness of the random numbers was significantly improved, and the bitstream passed standard randomness tests. The Pt/TaOx/Ta memristors fabricated in this work have fast programming/erasing speeds of ∼30 ns, suggesting a high random number throughput. The approach proposed here thus holds great promise for physically-implemented random number generation.

A spin-based true random number generator exploiting the stochastic precessional switching of nanomagnets

In this paper, we propose a spin-based true random number generator (TRNG) that uses the inherent stochasticity in nanomagnets as the source of entropy. In contrast to previous works on spin-based TRNGs, we focus on the precessional switching strategy in nanomagnets to generate a truly random sequence. Using the NIST SP 800-22 test suite for randomness, we demonstrate that the output of the proposed TRNG circuit is statistically random with 99% confidence levels. The effects of process and temperature variability on the device are studied and shown to have no effect on the quality of randomness of the device. To benchmark the performance of the TRNG in terms of area, throughput, and power, we use SPICE (Simulation Program with Integrated Circuit Emphasis)-based models of the nanomagnet and combine them with CMOS device models at the 45 nm technology node. The throughput, power, and area footprints of the proposed TRNG are shown to be better than those of existing state-of-the-art TRNGs. We identify the optimal material and geometrical parameters of the nanomagnet to minimize the energy per bit at a given throughput of the TRNG circuit. Our results provide insights into the device-level modifications that can yield significant system-level improvements. Overall, the proposed spin-based TRNG circuit shows significant robustness, reliability, and fidelity and, therefore, has a potential for on-chip implementation.

Entropy and Energy Bounds for Metastability Based TRNG with Lightweight Post-Processing

On-chip True Random Number Generators (TRNG) are important cryptographic primitives in a variety of applications. In advanced CMOS process technologies, intra-die variations in transistor parameters bias the TRNG and degrade the statistics of the bit stream generated. In this work, we present a stochastic model for metastability based TRNG circuit incorporating both the impact of intra-die variations and thermal noise. The stochastic model is used to estimate the expected entropy out of a TRNG at a given process corner for variations in channel length and threshold voltage. We use the stochastic model to study the impact of variations on three lightweight post-processing techniques: von Neumann corrector, XOR function, and PRESENT cipher. The expected bit rate out of von Neumann corrector, number of XOR stages required for entropy extraction and the number of iterations for using PRESENT encryption are estimated for various process corners using the probabilistic entropy values. These analyses are further extended to different device sizing and operating voltage to explore the optimum trade-off between entropy extraction and energy overhead. A combination of HSPICE circuit simulation using 32 nm Predictive Technology models and stochastic modeling in MatLab show that XOR function and von Neumann corrector have an energy overhead ranging from 0.012pJ/bit to 0.15pJ/bit at the cost of decreased yield and bit-rate respectively. PRESENT cipher provides robust entropy extraction by increasing the number of encryption iterations from 1 for $\mu/\sigma(Leff) to 3 for $\mu/\sigma(Leff)>8\%$ . With a maximum of 2.52pJ/bit PRESENT provides a more energy efficient solution compared to AES for entropy extraction in power constrained applications.