Design Of Tripler Research Articles

Multi-Mode 60-GHz Radar Transmitter SoC in 45-nm SOI CMOS

This article introduces an architecture for a millimeter-wave multi-mode radar transmitter IC, which supports three key radar waveforms: 1) continuous-wave (CW/FMCW); 2) pulse; and 3) phase-modulated continuous-wave (PMCW), all from a single front end. The proposed IC, implemented in a 45-nm CMOS silicon-on-insulator (SOI) process for operation in the 60-GHz band, integrates a broadband frequency tripler, a two-stage pre-amplifier, two power mixers, and mixed-signal baseband waveform generation circuitry. The transmitter radar operation in multiple modes is enabled by configuring the power mixers and the associated waveform baseband circuitry. An important advantage of this approach is that the overall signal bandwidth, a key performance metric in radar, is limited only by the RF output nodes in pulse generation. A novel broadband frequency tripler design technique based on a current-reuse topology is also proposed for LO generation with >59% output fractional bandwidth. On-wafer measurement results for the full TX IC in CW mode show an average output power of 12.8 dBm from 54 to 67 GHz with a peak power of 14.7 dBm and the harmonic rejection ratio >27 dB. The measurement in pulse mode demonstrates programmable pulsewidth from 20 to 140 ps, which translates to >40-GHz radar signal bandwidth. The PMCW mode operation is also demonstrated in this case with 10-Gb/s PRBS modulated radar signal. The IC consumes 0.51 W and occupies $2.3\times 0.85$ mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of die area excluding pads.

기본 주파수 불요파를 억제한 30 GHz 주파수 3체배기 설계

기본 주파수 불요파를 억제한 30 GHz 주파수 3체배기 설계

Graphene frequency tripler design using reflector networks

Graphene frequency tripler design using reflector networks

Fundamental analysis of harmonic reflection in microwave frequency triplers

Harmonic reflection is a vital technique for microwave frequency multiplier design, including the design of frequency triplers. In this article, principles of frequency tripler design with reflector networks are analyzed via harmonic-balance simulation of an idealized MESFET/HEMT transistor model. The use of an idealized model allows fundamental mechanisms of 3f0 output power and conversion-gain improvement via reflector networks to be characterized. Several reflector configurations are analyzed including: a 3f0 input reflector; a f0 output reflector; and a combination of both reflectors. The effects of reflector offset length on tripler performance are analyzed in terms of conversion gain, output power, reflected power, and time-domain waveforms. As a result of this work, a greater understanding of harmonic-reflector networks and their importance to tripler design is achieved. © 2006 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2006.

Design of W-Band Tripler

This paper describes a high performance W-band tripler with a novel structure. Input frequency is 25-36.7 GHz, output frequency 75-110 GHz, input power is 20dBm and conversion loss 16 dB. It can extend microwave signal to W-band (adding in Ka-band doubler). In the design, we give some approaches to achieve high band performances.