Triple Modular Redundancy Design Research Articles

Impact of TMR design layouts on single event tolerance in SRAM-based FPGAs

For highly reliable applications in mission critical systems, the Triple Modular Redundancy (TMR) technique is believed to be a common and effective approach to mitigate Single Event Upsets (SEUs) in Field Programmable Gate Arrays (FPGAs). In one of our neutron test campaigns, we observed an increase of 53.8% in single event tolerance of our optimized Fast Fourier Transform (FFT) design compared with the baseline (i.e., the traditional FFT design), while the increase of the TMR'd optimized FFT design is only 30.8% compared with the baseline. Although it is believed that Multiple-Cell Upsets (MCUs) poses a negative impact on the single event performance of TMR, the results of the TMR'd optimized FFT design are far from our expectations. A large number of preliminary simulations confirm that layout changes have a significant impact on the Multiple-Bit Upsets (MBUs) sensitivity of TMR'd design. This is because in the layout obtained through automatic placement and routing, these replicated modules of the TMR are interlaced with each other. Therefore, MBUs are more likely to induce domain-crossing events and affect two or more TMR modules. To further harden the TMR'd design, either putting three identical circuits of the TMR'd design into three independent blocks or using Dynamic Partial Reconfiguration (DPR) is demonstrated effective in mitigating MBUs in Static Random-Access Memory (SRAM)-based FPGAs.

Strategies for Removing Common Mode Failures From TMR Designs Deployed on SRAM FPGAs

Triple modular redundancy (TMR) with repair has proven to be an effective strategy for mitigating the effects of single-event upsets within the configuration memory of static random access memory field-programmable gate arrays. Applying TMR to the design successfully reduces the design's neutron cross section by 80×. The effectiveness of TMR, however, is limited by the presence of single bits in the configuration memory which cause more than one TMR domain to fail simultaneously. We present three strategies to mitigate against these failures and improve the effectiveness of TMR: incremental routing, incremental placement, and striping. These techniques were tested using both fault injection and a wide spectrum neutron beam with the best technique offering a 400× reduction to the design's sensitive neutron cross section. An analysis from the radiation test shows that no single bits caused failure and that multicell upsets were the main cause of failure for these mitigation strategies.

Dynamic SEU Sensitivity of Designs on Two 28-nm SRAM-Based FPGA Architectures

Two field-programmable gate array (FPGA) designs are tested for dynamic single event upset (SEU) sensitivity on two different 28-nm static random access memory-based FPGAs—an Intel Stratix V and a Xilinx Kintex 7 FPGA. These designs were tested in both a conventional unmitigated version and a version to tolerate SEUs with feedback triple modular redundancy (TMR). The unmitigated design sensitivity and the low-level device sensitivity were found to be similar between the devices through neutron radiation testing. Results also show that feedback TMR and configuration scrubbing benefit both designs on both FPGAs. While TMR is helpful, the benefit of TMR depends on the design structure and the device architecture. TMR and scrubbing reduced dynamic SEU sensitivity by a factor of 4– $54\times $ .

RASP-TMR: An Automatic and Fast Synthesizable Verilog Code Generator Tool for the Implementation and Evaluation of TMR Approach

Triple Modular Redundancy (TMR) technique is one of the most well-known techniques for error masking and Single Event Effects (SEE) protection for the FPGA designs. These FPGA designs are mostly expressed in hardware descrip-tion languages, such as Verilog and VHDL. The TMR technique involves triplication of the design module and adding the majority voter circuit for each output port. Building this triplication scheme is a non-trivial task and requires a lot of time and effort to alter the code of the design. In this paper, the RASP-TMR tool is developed and presented that has functionalities to take a synthesizable Verilog design file as an input, parse the design and triplicate it. The tool also generates a top-level module in which all three modules are instantiated and finally adds the proposed majority voter circuit. This tool, with its graphical user interface, is implemented in MATLAB. The tool is simple, fast and user-friendly. The tool generates the synthesizable design that facilitates the user to evaluate and verify the TMR design for FPGA-based systems. A simulation scenario is created using Xilinx ISE tools and ISim simulator. Different fault models are examined during simulations such as bit-flip and stuck at 1/0. The results using various benchmark designs demonstrate that the tool produces synthesizable code and the proposed majority voter logic perfectly masks the error/failure.

Fault-tolerant analysis of TMR design with noise-aware logic

Due to the effect of thermal noise, ground bounce and process variations in nanometer process, the behavior of any logical circuit becomes increasingly probabilistic. In this paper, based on the noise model [5] on the input and output nodes of a probabilistic CMOS (PCMOS) gate, the correctness probabilities of four PCMOS primitive gates, NOT, NAND, NOR and XOR, can be firstly computed. Based on the concept of the probabilistic transfer matrices (PTMs) and the corresponding operations on PTMs for the serial and parallel compositions of the components in a well-formed circuit, the correctness probability of the output in a 3-input PCMOS majority circuit in a triple modular redundancy (TMR) design can be further computed. For a given circuit with smaller error, it is well known that a TMR design has good fault-tolerant characterization and the correctness probability of the original output is converged to 1. Under the use of noise-aware logic in a TMR design, it is obvious that the fault-tolerant characterization of a TMR design is degraded and the correctness probability of the original output is not converged to 1. The experimental results show that the improvement region of the correctness probability of the original output will be narrowed due to the noise effect on the gates in a 3-input PCMOS majority circuit.

Single event upset mitigation techniques for FPGAs utilized in nuclear power plant digital instrumentation and control

Field programmable gate arrays (FPGAs) are integrated circuits being increasingly used for digital instrumentation and control (I&C) in nuclear power plants (NPPs) because of low cost, re-configurability and low design turn-around time. However, to ensure reliability, proper design techniques must be employed since the memory and logic in FPGAs are susceptible to single event upsets (SEUs). Triple modular redundancy (TMR) has become a common SEU mitigation design technique because of its straightforward implementation and reliable results. Partitioned TMR approaches are introduced in this paper, and formulae derived indicate that the maximum probability of two simultaneous errors [ P E] max is inversely proportional to the number of logic partitions in a TMR design, when each redundant logic block in every logic partition has the same number of sensitive nodes. However, the maximum logic partitioning design cannot completely eliminate the possibility of two simultaneous upsets. For the example test circuit it is found that [ P E] max is reduced dramatically from 66.67% for minimum logic partitioning to 4.44% for maximum logic partitioning. Because TMR introduces significant overhead due to its full hardware redundancy, a dual modular redundancy approach is also examined for application to less demanding situations. By comparative analysis this study reaches the conclusion that the maximum logic partitioning TMR implementation is the best solution for digital I&C applications in NPPs where obtaining robustness is of the highest importance, despite its higher area overhead.

SEU-Aware High-Level Data Path Synthesis and Layout Generation on SRAM-Based FPGAs

Although triple modular redundancy (TMR) has been widely used to mitigate single event upsets (SEUs) in static random access memory-based field-programmable gate arrays (FPGAs), SEU-caused bridging faults between the triplicated modules do not guarantee the correctness of TMR designs under all SEUs. In this paper, we present a novel computer-aided design flow for redundancy-based applications on FPGAs in order to mitigate the impact of SEUs in the configuration bitstreams. We introduce the notions of modular redundancy conflicts and vulnerability-gap conflicts which maintain the fundamental assumption underlying the integrity of redundancy-based designs (i.e., self-containment of SEU-induced faults within a single replica of redundant resources). When the impact of SEU-induced bridging faults is considered in high-level synthesis as well as physical synthesis, on average more than 30% improvement in the number of potential SEU-induced bridging faults can be reached as well as improvements in the performance and area utilization, compared to post-synthesis TMR, in which the voters are applied to the feedback structures in the circuit. Compared to the extreme case of post-synthesis TMR in which the voters are applied at the end of every configurable logic block, we reach 38% (26%) improvement in performance(area) of the implemented circuits.

Monte Carlo Analysis of the Effects of Soft Errors Accumulation in SRAM-Based FPGAs

Single event effects in SRAM-based FPGAs have been widely studied and there is a variety of mitigation techniques that can be used in order to achieve a complete fault tolerance. In this scenario, multiple faults are becoming a concern and new methodologies have to be developed in order to evaluate the effects of fault accumulation. In this paper a new Monte Carlo based methodology is used to evaluate soft errors accumulation in the configuration memory of triple modular redundancy designs implemented in SRAM-based FPGAs. Analytical predictions are confirmed by means of fault injection experiments.

A new reliability-oriented place and route algorithm for SRAM-based FPGAs

The very high integration levels reached by VLSI technologies for SRAM-based field programmable gate arrays (FPGAs) lead to high occurrence-rate of transient faults induced by single event upsets (SEUs) in FPGAs' configuration memory. Since the configuration memory defines which circuit an SRAM-based FPGA implements, any modification induced by SEUs may dramatically change the implemented circuit. When such devices are used in safety-critical applications, fault-tolerant techniques are needed to mitigate the effects of SEUs in FPGAs' configuration memory. In this paper, we analyze the effects induced by the SEUs in the configuration memory of SRAM-based FPGAs. The reported analysis outlines that SEUs in the FPGA's configuration memory are particularly critical since they are able to escape well-known fault masking techniques such as triple modular redundancy (TMR). We then present a reliability-oriented place and route algorithm that, coupled with TMR, is able to effectively mitigate the effects of the considered faults. The effectiveness of the new reliability-oriented place and route algorithm is demonstrated by extensive fault injection experiments showing that the capability of tolerating SEU effects in the FPGA's configuration memory increases up to 85 times with respect to a standard TMR design technique