Triangular Systolic Array Research Articles

Hardware Implementation of the Preprocessing QR-Decomposition for the Soft-Output MIMO Detection With Multiple Tree Traversals

Compared with the single tree detector, the layered orthogonal lattice detector (LORD), developed by Siti et al. , is a well-known soft-output multiple input multiple output detector to exploit ${M}$ parallel tree traversals to deliver data with ${M}$ times of detection throughput rate. The preprocessing QR-decomposition (QRD) of the ${M}$ -by- ${M}$ channel matrix for the single tree detector is of complexity proportional to ${M^{3}}$ . However, the preprocessing QRD for the LORD needs to compute the ${M}$ permuted channel matrices that are constructed from the original ${M}$ -by- ${M}$ channel matrix through the root conditioning criterion. The original LORD algorithm for this root conditioning QRD (RC-QRD) relies on the Gram-Schmidt orthogonalization and is of complexity proportional to ${M^{4}}$ for large ${M}$ . In this brief, we apply the Givens rotation and take advantage of the relationships among the ${M}$ permuted matrices to develop an RC-QRD algorithm with complexity proportional to ${M^{3}}$ . Furthermore, when ${M}$ is large, our proposed RC-QRD algorithm requires the number of real Givens rotations about 1.8 times necessary for computing a conventional matrix QRD. Also, for ${M=4}$ , our proposed RC-QRD hardware architecture requires gate count 2.1 times that required by the conventional triangular systolic array to compute a matrix QRD. Accordingly, with only about two times of complexity for the preprocessing RC-QRD, the LORD is able to perform ${M}$ tree traversals to deliver data with ${M}$ times of throughput rate.

Hardware-Efficient QR-Decomposition Using Bivariate Numeric Function Approximation

Bivariate function approximation has proven its feasibility in terms of hardware-efficient arithmetic signal processing. However, its impact on high performance QR decomposition (QRD) has only been roughly studied so far. In this paper, a novel hardware architecture for Givens-Rotation-based QRD is proposed targeting hardware efficient signal processing. To this end, an ingenious triangular systolic array structure is considered. Complex-valued matrices are efficiently processed by means of a sophisticated bivariate numeric function approximation methodology. In order to get a comprehensive insight in the performance, exhaustive evaluation is carried out with a modern multi-antenna wireless communication system. In detail, the proposed QRD hardware architecture is used in a suitable channel pre-coding setup. For a meaningful proof-of-concept, our work is evaluated on several levels of the computing stack. In addition, our design is implemented and physically synthesized in a state-of-the-art 65-nm Taiwan Semiconductor Manufacturing Company technology and compared with other publications. The results indicate our approach to be a powerful solution for hardware-based QRD, especially in terms of energy and area requirements.

Givens rotation‐based QR decomposition for MIMO systems

QR decomposition is an essential operation in various detection algorithms utilised in multiple-input multiple-output (MIMO) wireless communication systems. This study presents a Givens rotation-based QR decomposition for 4 × 4 MIMO systems. Instead of performing QR decomposition by coordinate rotation digital computer (CORDIC) algorithms, LUT compression algorithms are employed to rapidly evaluate the trigonometric functions. The proposed approach also provides greater accuracy compared with the CORDIC algorithms. QR decomposition is performed by complex Givens rotations cascaded with real Givens rotations. In complex Givens rotations, a modified triangular systolic array is adopted to reduce the delay units of the design and hence, reducing the hardware complexity. The proposed QR decomposition algorithm is implemented in TSMC 90 nm CMOS technology. It achieves the throughput of 53.5 million QR decompositions per second when operating at 214 MHz.

Hardware Architecture Based on Parallel Tiled QRD Algorithm for Future MIMO Systems

QR decomposition (QRD) has been a vital component in the transceiver processor of future multiple-input multiple-output (MIMO) systems, in which antenna configuration will be more and more flexible. Therefore, the QRD hardware architecture in the future MIMO systems should be more flexible to meet various antenna configurations. Unfortunately, the existing QRD hardware architectures mainly focus on the matrix of one or several fixed sizes. This paper presents a new triangular systolic array QRD hardware architecture based on parallel tiled QRD algorithm to decompose an $ {8}\times {8}$ real matrix. The designed hardware architecture is flexible and can be used in various MIMO systems, in which the number of antennas is smaller than 4. This paper also proposes a modified algorithm for the bottleneck operations of parallel tiled QRD algorithm to reduce the hardware overhead. To further reduce the hardware overhead, the Newton–Raphson algorithm is adopted in the proposed algorithm. The implementation results show that the normalized processing latency performance and the normalized processing efficiency performance of the designed QRD hardware architecture both are better than most of the existing QRD hardware architectures. To the best of our knowledge, the hardware architecture presented in this paper achieves the superior normalized QRD rate performance to the existing QRD hardware architectures.

QR decomposition architecture using the iteration look‐ahead modified Gram–Schmidt algorithm

QR decomposition is extensively adopted in multiple-input–multiple-output orthogonal frequency-division multiplexing wireless communication systems, and is one of the performance bottlenecks in lots of high-performance wireless communication algorithms. To implement low processing latency QR decomposition with hardware, the authors propose a novel iterative look-ahead modified Gram–Schmidt (ILMGS) algorithm based on the traditional modified Gram–Schmidt (MGS) algorithm. They also design the corresponding triangular systolic array (TSA) architecture with the proposed ILMGS algorithm, which only needs n time slots for a n × n real matrix. For reducing the hardware overhead, they modify the TSA architecture into an iterative architecture. They also design a modified iterative architecture to further reduce the hardware overhead. The implementation results show that the normalised processing latency of the modified iterative architecture based on the proposed ILMGS algorithm is 1.36 times lower than the one based on the MGS algorithm. To the best of the authors’ knowledge, the designed architecture achieves the superior latency performance than the existing works.

Multiplexing QR Decomposition Architecture Using the Givens-Rotation Algorithm for Adaptive Beamforming System

When the number of arrays increases, the triangular systolic array for QR decomposition of the received data matrix has an increasing significantly hardware resource consumption. In order to reduce the hardware cost, the triangular systolic array (TSA) architecture could be modified into a multiplexing architecture called MQRD which could call the same module at the different time. Then MQRD was designed and simulated on the software ISE. More, MQRD was added to the adaptive beanforming system to study its computing performance. The results showed that MQRD not only kept the numerical stability and scaled well, but also reduced the hardware resource cost efficiently. Theoretical analysis and simulation results show that MQRD can reduce hardware cost efficiently. So, MQRD is a better choice than TSA in the multi-antenna system.

Block-Wise QR-Decomposition for the Layered and Hybrid Alamouti STBC MIMO Systems: Algorithms and Hardware Architectures

Unlike the channel matrix in the spatial division multiplexing (SDM) multiple-input multiple-output (MIMO) communication system, the equivalent channel matrix in the layered Alamouti space-time block coding (STBC) MIMO system comprised 2-by-2 Alamouti sub-blocks. One novel property, found by Sayed about the QR-decomposition (QRD) of this equivalent channel matrix is that the produced Q- and R-matrices are also matrices with Alamouti sub-blocks. Taking advantage of this property, we propose a new block-wise complex Givens rotation (BCGR) based algorithm and a triangular systolic array (TSA) to compute the QRD of the equivalent channel matrix in an Alamouti block by block manner. Implementation results reveal that our new TSA can compute QRDs of 4-by-4 equivalent channel matrices faster than any architecture that has been developed for the SDM MIMO system. This property of fast QRD makes our TSA very attractive for the layered Alamouti STBC MIMO system combined with the orthogonal frequency division multiplexing. Our new BCGR based approach can also be applied to the hybrid Alamouti STBC MIMO system, which is also a system with equivalent channel matrix consisting of Alamouti sub-blocks.

Implementation of Unitary Music Algorithm Using Xilinx System Generator

The MUltiple SIgnal Classification MUSIC algorithm is a kind of DOA (Direction Of Arrival) estimation technique based on eigenvalue decomposition, which is also called subspace-based method [5]. In addition of its super resolution capability, MUSIC is very suitable for integration on logic circuit devices such as FPGAs (Field Programmable Gate Array).this paper proposes an implementation of unitary MUSIC algorithm using Xilinx System Generator (XSG). The design proposed uses CORDIC (COordinate Rotation DIgital Computer) -based Triangular Systolic Array for QR- decomposition to deal with EVD (eigenvalue decomposition). The MUSIC spectrum is computed with spatial DFT (Discrete Fourier Transform) using FFT block offered by Simulink- Xilinx blockset library. The performance of eight elements antenna array system was obtained and discussed.

RECURSIVE QR DECOMPOSITION ARCHITECTURE FOR MIMO-OFDM DETECTION SYSTEMS

This paper presents a modified implementation of QR decomposition for multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM) detection based on the Givens rotation method. The QR decomposition hardware is constructed using the coordinate rotation digital computer (CORDIC) algorithm operating with fewer gate counts and lower power consumption than do triangular systolic array (TSA) structures. Accurate signal transmission is essential to wireless communication systems. Thus, a more effective data detection algorithm and precise channel estimation method play vital roles in MIMO systems. Implementing data detection with QR decomposition helps reduce the complexity of MIMO-OFDM detection. Implementation results reveal that the proposed recursive QR decomposition (RQRD) architecture has lower clock latency than do TSA structures, and has a smaller hardware area than do Gram–Schmidt structures.

Efficient Implementation of QR Decomposition for Gigabit MIMO-OFDM Systems

This paper presents a VLSI architecture of QR decomposition for 4×4 MIMO-OFDM systems. A real-value decomposed MIMO system model is handled and thus the channel matrix to be processed is extended to the size of 8×8. Instead of direct factorization, a QR decomposition scheme by cascading one complex-value and one real-value Givens rotation stages is proposed, which can save 44% hardware complexity. Besides, the requirement of skewed inputs in the conventional QR-decomposition systolic array is eliminated and 36% of delay elements are removed. The real-value Givens rotation stage is also constructed in a form of a stacked triangular systolic array to match with the throughput of the complex-value one. Hardware sharing is considered to enhance the utilization. The proposed design is implemented in 0.18-μm CMOS technology with 152K gates. From measurement, the maximum operating frequency is 100 MHz. It generates QR decomposition results every four clock cycles and accomplishes continuous projection every clock cycle to support MIMO detection up to 2.4 Gb/s. The measured power consumption is 318.6 mW and 219.6 mW for QR decomposition and projection, respectively, at the highest operating frequency. From the comparison, our proposed design achieves the highest throughput with high efficiency.

Iterative <formula formulatype="inline"><tex Notation="TeX">$QR$</tex> </formula> Decomposition Architecture Using the Modified Gram–Schmidt Algorithm for MIMO Systems

Implementation of an iterative QR decomposition (QRD) (IQRD) architecture based on the modified Gram-Schmidt (MGS) algorithm is proposed in this paper. A QRD is extensively adopted by the detection of multiple-input-multiple-output systems. In order to achieve computational efficiency with robust numerical stability, a triangular systolic array (TSA) for QRD of large-size matrices is presented. In addition, the TSA architecture can be modified into an iterative architecture that is called IQRD for reducing hardware cost. The IQRD hardware is constructed by the diagonal and the triangular process with fewer gate counts and lower power consumption than TSAQRD. For a 4 t 4 matrix, the hardware area of the proposed IQRD can reduce about 41% of the gate counts in TSAQRD. For a generic square matrix of order m IQRD, the latency required is 2m - 1 time units, which is based on the MGS algorithm. Thus, the total clock latency is only 10 m - 5 cycles.

Parametric minimum hardware QR-factoriser architecture for V-BLAST detection

The authors introduce a new architecture for the core processor for a V-BLAST detector. This architecture uses only two low complexity CORDIC processors for QR factorisation. The parameterised feature of the controller and address generator blocks provides a scalable architecture for the implementation of QR factorisation for a square matrix of any dimension. The reduced hardware complexity of the processors and its simple parameterised controller are two outstanding features of the architecture, resulting in a more suitable alternative architecture for QR factorisation than triangular systolic arrays. A comprehensive analysis of parameters influencing the hardware implementation and their effects on the error performance of the V-BLAST detector has been presented. The implementation of the proposed architecture on an Altera Stratix FPGA device results in a very small critical path delay. This provides a platform for the fast matrix triangularisation for applications requiring high data rates such as MIMO V-BLAST detectors. The maximum throughput values of up to 367 Mbit/s are reachable using this novel QR-factorisation architecture for the V-BLAST detector.

A systolic array for the parallel solution of block trid1agonal linear systems (Sats)

In this paper the parallel solution of block tridiagonal linear systems derived from the finite difference/element discretisation of 2D/3D elliptic partial differential equations which occur frequently in scientific and engineering applications is presented. The direct solution by the Gaussian elimination algorithm is used and a parallel architecture designed employing a systolic array (SATS) which comprises of triangular and rectangular systolic arrays to perform the block triangularisation of the system. The block triangular system is then solved by a pipeline using local memory systems. The results show that when the system order is > 10 then the speedup of the parallel system is significant

Systolic computation of QZ matrix decomposition

Four new triangular systolic arrays for QZ matrix decomposition based on the block Givens and Householder transformations are described. Their performance is compared with the traditional point rotator and point reflector for the QR matrix decomposition. The comparison is based on the detailed discussion of the length of global time step Δ t which synchronizes the array, the number of required processors and the area defined by the vertical and horizontal links used in the array for the data pipelining. It turns out that the most efficient array for the QZ matrix decomposition is the one which implements the block Givens rotation with an encoder and decoder in the diagonal and nondiagonal processors, respectively. This array is almost perfectly balanced as opposed to the well known triangular array for QR matrix decompositon designed by W. M. Gentleman and H. T. Kung.

Fault-tolerant QRD recursive least squares

The authors present an algorithm-based fault tolerant scheme for recursive least squares, appropriate for applications in adaptive signal processing. The technique is closely focused on the Gentleman-Kung-McWhirter triangular systolic array architecture for QR decomposition. Assuming that the array is subject to transient faults, widely separated in time and each affecting a single processor, an algorithm is given that corrects the full triangular array with a computational overhead equivalent, on average, to the interpolation of a single extra vector into the data stream. No output residuals are lost in the fault recovery. The analysis is extended to a fault-tolerant algorithm for linearly constrained QR decomposition.

Parallel direct solution for P-cyclic matrix systems

In this paper, the parallel solution of the P-cyclic matrix system derived from the finite difference/element discretisation of the two point boundary-value problem is developed although the P-cyclic systems also arises in many other stochastic applications. The direct solution by the Gaussion elimination method is developed into an algorithmic procedure which is used for solving the P-cyclic system. A parallel architecture is then designed based on the algorithm to speedup the solution. The architecture employs a systolic array, which comprises a triangular systolic array and a rectangular systolic array, to perform the block triangularisation of the P-cyclic system. The block triangular system is solved by a local memory system in parallel. The results show that when the order of the differential equation is larger than 10, the speedup of the parallel system is significant. The efficiency of the architecture can be up to more than 50%.

Recursive triangular array ladder algorithms

Two recursive-least-squares ladder algorithms for implementation on triangular systolic arrays are presented. The first algorithm computes transversal forward/backward predictor coefficients, ladder reflection coefficients, and forward/backward residual energies. This algorithm has a complexity of three multiplications and additions per rotational (triangular array) element. A second algorithm is presented that facilitates the computation of only the ladder reflection coefficients and the forward/backward residual energies at a cost of two multiplications and additions per rotational element. This way, both algorithms are computationally more efficient than the traditional recursive QR decomposition (Gentleman and Kung array) for any order. The second algorithm is more efficient than Cioffi's pipelineable linear array fast QR adaptive filter for an order of less than 22 in the prewindowed case, and more efficient than the fast QR for an order of less than 43 in the more general covariance case. A comparison of the presented algorithms and the prominent QR methods is given. The algorithms remain unchanged and the number of arithmetic operations is not increased when finite duration windows are used. The algorithms are based entirely on numerically stable and robust covariance recursions. >

Multichannel recursive least squares adaptive filtering without a desired signal

The author presents a pair of adaptive QR decomposition-based algorithms for the adaptive mixed filter in which no desired signal is available, but the signal-to-data cross-correlation vector is known. The algorithms are derived by formulating the recursive mixed filter as a least-squares problem and then applying orthogonal QR-based techniques in its solution. This leads to algorithms with the performance, numerical, and structural advantages of the RLS/QR algorithm, but without the requirement of a desired signal. Both Givens and square-root-free Givens rotations are used in implementing the recursive QR decomposition. Because of their structural regularity, the algorithms are easily implemented by triangular systolic array structures. Simulations show that these algorithms require fewer computations and less precision than recursive sample matrix inversion approaches.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A triangular systolic array for the discrete-time deconvolution

The principles of convolution and deconvolution known for linear systems have been applied to many engineering problems such as electromagnetic inverse scattering, seismology, system identifications, pattern recognition, etc. For applications involving a large amount of data, systolic array processing is attractive for efficiency and reduction of the data-processing time. Systolic arrays for discrete-time convolution have been previously developed. A triangular systolic array, consisting of two types of processing cells, is presented for the discrete-time deconvolution. The functions of the processing cells and their interconnections are described. The pipeline architecture of the triangular systolic array is derived from the recursive pattern of deconvolution. Cell computations and data flow within the systolic array are synchronized by a single global clock. >

Algorithmic fault tolerance for matrix operations on triangular arrays

In this paper the technique of algorithm-based fault tolerance which is used to detect and correct transient or permanent hardware faults by checksum matrices is reconsidered for triangular systolic arrays. Linear error detecting arrays are developed for both matrix product and triangular factorisation and are shown to interface neatly with triangular schemes. The overheads associated with error detecting redundancy is offset by hardware reduction due to the folding of the array to produce triangular rather than the standard hex connected arrays. The result is shown to be improved efficiency and area efficient fault tolerant arrays.