Tri-gate Nanowire Research Articles

Analysis of coupling effect between TID and SET in SOI Tri-Gate nanowire field-effect transistors

This study investigates the response of nanowire field-effect transistors (NWFETs) to total ionizing dose (TID), single-event transient (SET), and their coupling effects in junctionless (JL), inversion (IM), and junctionless accumulation (AC) modes. The degradation of the three modes under irradiation and the effect of device bias configuration on the electrical properties of NWFETs are analyzed, and the different effects of SET on the three modes are compared. On this basis, the influence of TID on SET current generation and the charge collection mechanism are studied, and the changes in peak current, pulse width, and collected charge of transient current under different TIDs are compared. The results show that JL mode has the worst resistance to TID and SET coupling effects, followed by IM and AC modes.

Modeling of 1D confinement in FD-SOI trigate nanowires at deep cryogenic temperatures

Multi-gate FD-SOI qubit MOS devices were electrically characterized. At deep cryogenic temperatures and in linear regime, oscillations in both the current and the transconductance were observed above threshold. These are likely related to the formation of one-dimensional sub-bands in the silicon active region. A compact model taking into account a 1D density of states (DOS) has been developed in order to fathom how the 1D confinement influences both the inversion charge and the transconductance. The impact of temperature was shown to be crucial in order to distinguish the sub-bands contribution to the transconductance oscillations. Furthermore, the impact of drain voltage was also investigated, showing that the oscillations were smoothed out at high drain biases.

Enhancement-Mode InAlN/GaN Power MOSHEMT on Silicon With Schottky Tri-Drain Extension

This study demonstrates an enhancement-mode (E-mode) InAlN/GaN MOSHEMT on a silicon substrate with a Schottky tri-drain extension (STDE) to yield a large breakdown voltage ( $\text{V}_{\text {BD}}$ ) while maintaining a low on-resistance ( $\text{R}_{\text {on}}$ ). The E-mode operation is realized by a recessed tri-gate nanowire structure. The STDE functions as a drain-connected field plate (FP) to effectively distribute the electric field (E-field) around the drain contact edge, improving the $\text{V}_{\text {BD}}$ . Moreover, through the metal of the STDE directly contacting the 2-D electron gas (2-DEG) from the sidewalls, a low specific $\text{R}_{\text {on}}$ ( $\text{R}_{\text {on, sp}}$ ) is achieved. The proposed device with a gate-to-drain length ( $\text{L}_{\text {GD}}$ ) of $5~\mu \text{m}$ exhibits a threshold voltage ( $\text{V}_{\text {TH}}$ ) of +0.9 V, large maximum drain current ( $\text{I}_{\text {D, max}}$ ) of 815 ± 27 mA/mm, high $\text{I}_{\text {on}}/\text{I}_{\text {off}}$ ratio of 1010, steep subthreshold swing (SS) of 67 mV/decade, superior $\text{V}_{\text {BD}}$ of 830 V, and low $\text{R}_{\text {on, sp}}$ of 0.74 ± 0.04~\text{m}\Omega \cdot cm2. With $\text{L}_{\text {GD}}$ of $10~\mu \text{m}$ , a $\text{V}_{\text {BD}}$ of 1190 V is achieved, corresponding to a $\text{R}_{\text {on, sp}}$ of 1.39 ± $0.07~\text{m}\Omega \cdot$ cm2. These results reveal great potential for future E-mode power device applications.

Analysis of Nanowire Field-Effect Transistors SET Response: Geometrical Considerations

The single-event transient (SET) response of silicon-on-insulator (SOI) tri-gate silicon nanowires is investigated using direct measurements of current transients. The impact of nanowire geometry is discussed using the major SET characteristics: duration, amplitude, and integrated value. The experimental results demonstrate the key influence of the nanowire width on the generated current transients induced by heavy ion irradiations. Both Monte-Carlo calculations of deposited energy and Technology Computer Aided Design (TCAD) simulations give evidence of the SOI tri-gate silicon nanowires ability to mitigate generated current transients. TCAD calculations are used to discuss the impact of the main nanowire geometrical parameters which include the nanowire width, thickness, and gate length, on transient charge collection mechanisms in SOI nanowire field-effect transistors (NWFET). Thin and narrow NWFET designs enhance the control of the surrounding gate over the electrostatic potential into the nanowire. The onset of floating body effects induced by heavy ion strike is reduced which mitigates the SET generation.

Enhancement-Mode Tri-Gate Nanowire InAlN/GaN MOSHEMT for Power Applications

This letter demonstrates a novel enhancement-mode (E-mode) tri-gate nanowire InAlN/GaN MOSHEMT with ultrasonic spray pyrolysis deposition (USPD) deposited Al2O3 as the gate dielectric layer. The proposed device reveals a threshold voltage ( ${V}_{\text {TH}}$ ) of +2.3 V and a maximum drain current ( ${I}_{D, \text {max}}$ ) of 705 mA/mm. It also exhibits superior electrical performances, including a high ON-state/ OFF-state current ( ${I}_{ {{ \scriptscriptstyle {\text {ON}}}}}/{I}_{ {{ \scriptscriptstyle {\text {OFF}}}}}$ ) ratio of 109–1010, a steep subthreshold swing (SS) of 65 mV/decade, and a large breakdown voltage (BV) of 800 V with a leakage current of 0.7 $\mu \text{A}$ /mm while keeping a low-specific ON-resistance ( ${R}_{ {{ \scriptscriptstyle {\text {ON}}}}, \text {sp}}$ ) of 1.04 $\text{m}\Omega \cdot \text {cm}^{\text {2}}$ . This novel E-mode device presents a great potential for power device applications.

Investigations on the Geometry Effects and Bias Configuration on the TID Response of nMOS SOI Tri-Gate Nanowire Field-Effect Transistors

This paper investigates the total ionizing dose (TID) sensitivity of nanowire (NW) field-effect transistors (NWFETs). Both X-ray irradiations and self-consistent calculations of charge trapping in dielectrics are performed to study their TID response. First of all, the impact of the NW geometry is investigated. The NWFET TID behavior exhibits a strong dependence as a function of the NWs width while shortening the gate length does not significantly change the TID characteristics of optimized narrow NWFETs. Furthermore, the effect of the bias configuration used during irradiation is discussed to state if nMOS NWFETs could withstand significant amount of TID in several operation conditions.

Low Temperature Characterization of Hole Mobility in Sub-14nm Gate Length Si0.7Ge0.3 Tri-Gate pMOSFETs

We performed low temperature characterization of hole mobility in SiGe Trigate nanowires (NW) with gate length scaled down to 10nm. Trigate NWs with high-k/metal gate stack were fabricated on SOI wafers using solely optical lithography to design the wires with width down to 15nm. Drain current measurements are conducted within a cryogenic probe station enabling study on a 80K-350K temperature range. From these measurements we extracted the temperature dependence of the low field mobility μ0 for a wide range of gate lengths and NW widths using the Y-function method in order to cancel the influence of the mobility attenuation factor due to series resistances. The impact of the temperature over the mobility can be used to identify the dominant scattering mechanism in the channel. Overall, we observed that hole transport is predominantly limited by the extra scattering due to neutral defects in all devices with a gate length under 40 nm. Source/Drain implantations trace the origins of these defects. Consequently, these particular process steps should gain special care in the design of further node generation as they critically hinder charge mobility at that scale.

Strain effect on mobility in nanowire MOSFETs down to 10 nm width: Geometrical effects and piezoresistive model

The effect of strain on carrier mobility in triple gate Fully Depleted Silicon On Insulator (FDSOI) nanowires (NWs) is experimentally investigated through piezoresistance measurements. The piezoresitive coefficients have been extracted and analyzed for rectangular cross-section with varying aspect ratio (width vs. height). We propose an empirical model based on mobility separation between top and sidewall conduction surfaces of the NWs, and on the carrier density calculation in the cross-section of the NWs. The model allows fitting the piezoresistive coefficients and the carrier mobility for the different device geometries. We highlight an enhanced strain effect for Trigate nanowires with channel thickness below 11nm.

Experimental study of time-dependent dielectric breakdown in tri-gate nanowire transistor

We systematically investigate the size dependence of the time-dependent dielectric breakdown (TDDB) in a tri-gate nanowire transistor (NW Tr.). It is newly found that TDDB reliability is degraded in NW Tr. as compared with that in a planar transistor owing to the locally enhanced electric field at the NW corner. Moreover, in the region with a width (W) less than 40 nm, nanowire width reduction leads to a shorter time to gate dielectric breakdown indicating additional degradation of TDDB reliability in NW Tr. with smaller W. Although TDDB in three-dimensional (3D) MOS structures such as a trench MOS capacitor has already been reported, the size dependence of TDDB in scaled NW Tr. is firstly discussed in this paper since a trench capacitor is different from recent NW Tr. in structure, device size, gate dielectric thickness, and scaling effect on TDDB.

High Gamma Value 3D-Stackable HK/MG-Stacked Tri-Gate Nanowire Poly-Si FETs With Embedded Source/Drain and Back Gate Using Low Thermal Budget Green Nanosecond Laser Crystallization Technology

Three-dimensional sequentially stackable high- $k$ /metal-gate-stacked tri-gate nanowire poly-Si FETs with embedded source/drain (e-S/D) and back gate were demonstrated. The highly crystallized channel, fabricated by green nanosecond laser crystallization, chemical mechanical polish, and postsurface modification processes, enhances the electrical property of the tri-gate nanowire FET. The e-S/D structure reduces the contact and series resistances caused by the nanowire structure. Thus, the fabricated n/p-type tri-gate nanowire poly-Si FETs exhibit steep subthreshold swings (96/125 mV/decade), high ON-currents (232/110 $\mu \text{A}/\mu \text{m}$ ), and $I_{{\mathrm{\scriptscriptstyle {on}}}}/I_{\mathrm{\scriptscriptstyle {OFF}}}$ ratio ( $> 10^{5})$ . Furthermore, the independent back gate with thin back gate oxide can easily adjust the threshold voltage of the tri-gate nanowire transistor and results in high gamma value (>0.05) FET realizing sequentially stacked and low $V_{\mathrm {dd}}$ (0.6 V) operable inverter.

BSIM4 parameter extraction for tri-gate Si nanowire transistors

We investigated the BSIM4 parameter extraction procedure for tri-gate Si nanowire transistors with different geometries and fabrication processes. SPICE modeling tool was used to extract the parameter from Id–Vg to Id–Vd characteristics with liner and saturation region. Dependence of source/drain parasitic resistances on nanowire width and gate sidewall thickness can be observed on the extracted parameters. Furthermore, parasitic capacitance was extracted from three-dimensional TCAD simulation with our fabricated device structure. Single sets of parameters can reproduce I–V characteristics with Lg down to 35nm for n-channel nanowire transistors. It was found that the extracted parameters will be a useful tool for characterizing the circuit performance of nanowire transistor. Therefore, this procedure is applicable to extract the BSIM4 model parameters for NW Tr. as well as other multi-gate FETs.

Experimental Study of Random Telegraph Noise in Trigate Nanowire MOSFETs

Random telegraph noise (RTN) in trigate nanowire transistors (NW Tr.) is systematically studied with respect to the NW size dependence. Time to capture and emission, which is related to the characteristic of the traps, such as trap energy, is independent of NW size. On the other hand, noise amplitude increases as the NW size decreases showing the similar size dependence to the reported scaled planar Tr. In addition, RTN after hot-carrier injection (HCI) and negative bias stress (NBS) is studied. HCI and NBS induce additional carrier traps, which generate larger noise signals. Since the degradation by HCI or NBS is larger with narrower width, RTN after these stresses is found to be severer in the NW Tr.

Channel size dependence of low-frequency noise in tri-gate silicon nanowire transistors

We systematically study the channel size dependence of drain current noise amplitude in tri-gate silicon nanowire transistors (NW Tr.) by measuring a large number of samples with various parameters such as gate length (Lg), NW width (WNW), and NW height (HNW) down to 10 nm. The noise of NW Tr. with WNW < 20 nm rapidly increases with 1/WNW because an electron in a single trap on the NW channel blocks the entire current flow (bottleneck effects). The strength of bottleneck effects is determined solely by WNW not by HNW. The noise increase at narrow WNW is smaller in short-Lg Tr. (down to 15 nm).

Trigate nanowire MOSFETs analog figures of merit

This work studies, for the first time to our best knowledge, the perspectives of trigate nanowire (TGNW) MOSFETs for analog applications. An effect of nanowire width, length and orientation as well as frequency (up to 4GHz) and temperature (up to 225°C) on analog figures-of-merit (FoM) is analyzed. Benchmarking with other advanced devices such as ultra-thin body and BOX (UTBB) MOSFETs and SOI-based FinFETs is presented. TGNW MOSFETs are shown to be very promising for analog applications featuring high transconductance combined with high intrinsic gain. Only a slight reduction of device performance over the frequency and temperature ranges is observed.

Flat-band voltage and low-field mobility analysis of junctionless transistors under low-temperature

This paper presents the low-temperature characteristics of flat-band (VFB) and low-field mobility in accumulation regime (µ0_acc) of n-type junctionless transistors (JLTs). To this end, split capacitance-to-voltage (C–V), dual gate coupling and low-temperature measurements were carried out to systematically investigate VFB. Additionally, the gate oxide capacitance per unit area Cox and the doping concentration ND were evaluated as well. Accounting for the position of VFB and the charge based analytical model of JLTs, bulk mobility (µB) and µ0_acc were separately extracted in volume and surface conduction regime, respectively. Finally, the role of neutral scattering defects was found the most limiting factor concerning the degradation of µB and µ0_acc with gate length in planar and tri-gate nanowire JLTs.

P069 Effets d’un régime riche en acide α-linolénique sur le métabolisme secondaire de l’arginine

This paper presents experimental results on the effective electron mobility in heavily doped tri-gate nanowire junctionless SOI MOSFETs with various nanowire widths. Significant enhancement of the electron mobility in narrow nanowire devices, as compared to counterpart planar (wide) devices, having the same film thickness and doping, and as compared to the bulk silicon mobility with the same doping is demonstrated. This effect is attributed to the reduced impurity scattering in narrow nanowire devices. The obtained results are seen to be very important as low carrier mobility due to high doping was previously assumed to be the fundamental limitation of junctionless nanowire devices.

Experimental study of back gate bias effect and short channel effect in ultra-thin buried oxide tri-gate nanowire MOSFETs

We studied the relation between body effect factor and subthreshold slope in ultra-thin buried oxide tri-gate nanowire MOSFETs with various gate lengths, nanowire widths, and nanowire heights. As gate length decreases, body effect factor increases due to the enhancement and suppression of the short channel effect with positive and negative back gate bias voltage, respectively. The reduction of nanowire width leads to the decrease in both body effect factor and subthreshold slope resulting in trade-off relation, whereas better subthreshold slope and larger body effect factor were achieved by thinning nanowire height.

3D analysis of advanced nano-devices using electron and atom probe tomography

The structural and chemical properties of advanced nano-devices with a three-dimensional (3D) architecture have been studied at the nanometre scale. An original method has been used to characterize gate-all-around and tri-gate silicon nanowire transistor by combining electron tomography and atom probe tomography (APT). Results show that electron tomography is a well suited method to determine the morphological structure and the dimension variations of devices provided that the atomic number contrast is sufficient but without an absolute chemical identification. APT can map the 3D chemical distribution of the atoms in devices but suffers from strong distortions in the dimensions of the reconstructed volume. These may be corrected using a simple method based on atomic density correction and electron tomography data. Moreover, this combination is particularly useful in helping to understand the evaporation mechanisms and improve APT reconstructions. This paper demonstrated that a full 3D characterization of nano-devices requires the combination of both tomography techniques.

Scaling of high-κ/metal-gate TriGate SOI nanowire transistors down to 10 nm width

In this paper, TriGate nanowire (TGNW) FETs with high-κ/metal gate are studied as an alternative way to planar devices for the future CMOS technological nodes (14nm and beyond). The influence of Si film thickness (H) and nanowire width (W) on electrical performance of long- and short-channel devices are presented and discussed. We show that the transport properties in our TGNW are fully governed by the additive contributions of the (100) top surface and (110) sidewalls. As compared to wide planar devices, the improvement of electrostatic integrity (subthreshold slope and drain-induced-barrier-lowering) of scaled down TGNW FET is clearly demonstrated.

Scaling of Trigate nanowire (NW) MOSFETs to sub-7 nm width: 300 K transition to Single Electron Transistor

In this paper we show that on scaling nanowire width from 20nm down to sub-7nm regime, together with achieving excellent short channel effect control (DIBL=12mV/V for LG=20nm), we hit a dramatic transition in transport mechanism from monotonously increasing ID–VG of a FET to oscillating ID–VG of a Single Electron Transistor. This transition in transport mechanism is brought about by process induced channel potential variability. It poses a challenge to further scaling of nanowire MOSFETs. However, we show that it provides an exciting opportunity to cointegrate Single Electron Transistors with high-k/metal gate operating at room temperature (at VD=±0.9V) with the state-of-the-art nanowire MOSFETs enabling large scale manufacturing of Beyond Moore devices.