Trench Sidewall Research Articles

(Invited) Impacts of Anisotropic Material Properties on Performance of SiC Power Devices

Silicon carbide (SiC) has emerged as a wide bandgap semiconductor suitable for advanced high-voltage and low-loss power devices. Through rapid progress of both SiC material and device technologies in the last two decades, 600–3,300 V SiC power MOSFETs and Schottky barrier diodes are currently in volume production, demonstrating remarkable improvement of energy efficiency. So far, the 4H polytype of SiC (4H-SiC) has been exclusively used for fabrication of SiC electronic devices, owing to it superior physical properties and availability of large (150 mm diameter) and high-quality wafers. However, 4H-SiC exhibits significant anisotropy in physical, chemical, and interface properties, due to its unique hexagonal crystal structure. The authors have recently clarified several important anisotropic material properties of 4H-SiC and, in this paper, impacts of the anisotropic properties on performance of SiC power devices are overviewed. Since SiC power devices are fabricated as “vertical devices” on SiC(0001) wafers, the current mainly flows along <0001> and high voltage (i.e. high electric field) is applied along the same direction. Thus, carrier mobility and impact ionization coefficients along <0001> are key physical properties which determine the performance of SiC power devices. Regarding the mobility, the authors fabricated Hall-bar structures along <0001> and <1-100> side by side on custom-made SiC(11-20) epitaxial substrates. It turned out that the electron mobility along <0001> is about 15–20% higher than that along <1-100> (or <11-20>), the latter of which was ever measured in almost all the previous studies. The electron mobility along <0001> was determined in wide ranges of the donor density (5x1014–3x1018 cm-3) and temperature (200–600 K), and the highest mobility at room temperature ever reported (1210 cm2/Vs) was obtained along <0001> for a lightly-doped SiC epilayer. On the other hand, the hole mobility showed an opposite anisotropy: The hole mobility along <0001> is about 10–15% lower than that along <1-100>. The authors carefully considered the first Brillouin zone of 4H-SiC to interpret these mobility anisotropies and concluded that these anisotropies can be quantitatively explained by the anisotropy of effective mass, taking account of energy distribution of carriers. The impact ionization coefficients of electrons and holes along <0001> and <11-20> were also determined by analyzing photo-multiplication current of many different SiC pn diodes fabricated on (0001) and (11-20) substrates, respectively. Although the ionization coefficients of holes along both the directions (<0001> and <11-20>) and the coefficient of electrons along <11-20> are all similar, the coefficient of electrons along <0001> is two- or three-orders-of-magnitude smaller. This unusually small impact ionization coefficient of electrons along <0001> can be explained by considering hot electrons in the unique conduction band (E – k dispersion in the first Brillouin zone) of 4H-SiC. As a result, the critical electric field, which determines the junction breakdown, along <0001> is significantly higher than that expected from the bandgap of SiC. Thus, the anisotropies of both electron mobility and critical electric field (both are higher along <0001>) give 4H-SiC vertical devices fabricated on (0001) wafers much superior performance compared with previous predictions published in literature. In SiC power MOSFETs with 600–1200 V class blocking voltage, the MOS channel resistance is the major component in the total on-resistance, because the drift resistance of the voltage-blocking layer is extremely low (< 3x10-4 Ω cm2) with SiC. The authors discovered that MOS channels on (11-20) and (1-100), both of which are perpendicular to the (0001) wafer surface, show much higher mobility (about 110–120 cm2/Vs) than those on (0001) (about 40 cm2/Vs) in n-channel MOSFETs with a lightly-doped p-body, as far as appropriate nitridation is performed after gate oxide formation. The high mobilities on (11-20) and (1-100) are attributed to the lower density of interface states especially near the conduction band edge in the SiO2/SiC structure, which leads to less electron trapping and less Coulomb scattering at the interface. These results have promoted development of high-performance SiC trench MOSFETs, where the MOS channels are formed on the trench sidewalls. In recent years, the authors achieved a high mobility of over 130 cm2/Vs in n-channel MOSFETs with a heavily-doped p-body on these planes by using an original oxidation-minimizing process. Furthermore, a reasonably high mobility of over 25 cm2/Vs was obtained in p-channel SiC MOSFETs on (11-20) and (1-100), which is two-fold improvement compared with (0001) MOSFETs. Impacts of these high mobilities on SiC MOSFETs are discussed in detail.

Characterization of structural and mechanical properties of DLC films deposited on the surface of minute-scale 3D objects: Changes in the incident behavior of carbon ions

Diamond-like carbon (DLC) films have attracted great interest from the industry because they have beneficial mechanical properties such as low friction, high hardness, and wear resistance. DLC films have been used for the surface modification of various mechanical components, although many components that require surface treatments have complex three-dimensional (3D) surface structures. To date, 3D deposition of DLC films remains difficult using conventional methods. Particularly, uniform deposition technology on 3D components has not been developed for tetrahedral amorphous carbon (ta-C) films, which possess high CC sp3 bonds with high hardness. In this study, the filtered cathodic vacuum arc (FCVA) method was used to synthesize ta-C films on Si substrates placed on the sidewalls of trench-shaped and one-side tilted samples at various tilt angles and investigated their microstructure and hardness by Raman spectroscopy and nanoindentation. The results showed that the G peak position, full width at half maximum of G peak (FWHM (G)), and hardness of the ta-C film on the trench sidewall decreased as the depth from the top surface increased, similar to previous research. In contrast, ta-C films deposited on one-side tilted sample showed little depth dependence, and the film properties were determined by the tilt angle. We revealed that the film property dependence on the trench depth direction is due to the sputtered particles from the opposing trench sidewalls, resulting in graphitization of the film.

Controlled Anisotropic Wetting by Plasma Treatment for Directed Self-Assembly of High-χ Block Copolymers.

The directed self-assembly (DSA) of block copolymers (BCPs) is a promising next-generation lithography technique for high-resolution patterning. However, achieving lithographically applicable BCP organization such as out-of-plane lamellae requires proper tuning of interfacial energies between the BCP domains and the substrate, which remains difficult to address effectively and efficiently with high-χ BCPs. Here, we present the successful generation of anisotropic wetting by plasma treatment on patterned spin-on-carbon (SOC) substrates and its application to the DSA of a high-χ Si-containing material, poly(1,1-dimethylsilacyclobutane)-block-polystyrene (PDMSB-b-PS), with a 9 nm half pitch. Exposing the SOC substrate to different plasma chemistries promotes the vertical alignment of the PDMSB-b-PS lamellae within the trenches. In particular, a patterned substrate treated with HBr/O2 plasma gives both a neutral wetting at the bottom interface and a strong PS-affine wetting at the sidewalls of the SOC trenches to efficiently guide the vertical BCP lamellae. Furthermore, prolonged exposure to HBr/O2 plasma enables an adjustment of the trench width and an increased density of BCP lines on the substrate. Experimental observations are in agreement with a free energy configurational model developed to describe the system. These advances, which could be easily implemented in industry, could contribute to the wider adoption of self-assembly techniques in microelectronics, and beyond to applications such as metasurfaces, surface-enhanced Raman spectroscopy, and sensing technologies.

Epitaxial trench refill of 4H-SiC by chlorinated chemistry

Trench epitaxy of 4H-SiC is investigated with the supersaturation of chlorinated chemistry at a growth temperature of 1550 °C. Coupled with a lower growth temperature than has been previously reported, the integrity of the 4H-SiC trenches is retained and minimal rounding effects of H2 annealing prior to growth are observed. The system gives different growth rates of materials on the various crystal faces of the trenches and can be used to improve the refilling process, resulting in the reduced void formation. The addition of excessive levels of HCl can suppress trench epitaxy by reducing the growth rate on the sidewalls of trenches in favor of growth on the surface. The processes demonstrated offer a scalable and reproducible method to fabricate SiC-based superjunction device structures for applications in high voltage power electronics.

A High Channel Mobility and a Normally‐off Operation of a Vertical GaN Metal‐Oxide‐Semiconductor Field‐Effect Transistors using an AlSiO/AlN Gate Stack Structure on m‐plane Trench Sidewall

An AlSiO/AlN‐interlayer gate stack formed on c‐plane GaN metal‐oxide‐semiconductor (MOS) devices was previously developed to enhance the interface of the gate insulator. By utilizing this gate stack structure, a channel mobility of over 200 cm2 Vs−1 on c‐plane was obtained. However, the threshold voltage was negative because of the polarization charge at the AlN/GaN interface. This study extends the application of this gate stack structure to the nonpolar m‐plane, which is obtained from a trench sidewall. Both a high channel mobility of 150 cm2 Vs−1 and a threshold voltage of 1.3 V is successfully achieved, normally‐off operation. This achievement holds significant promise for the gate structure of a GaN trench‐gate MOS field‐effect transistor (MOSFET). The limiting factor of the channel mobility is Coulomb scattering in a low electric field, whereas surface roughness scattering is dominant in a higher field.

Trench-filling heteroepitaxy of [100]-oriented germanium arrays on (001) silicon substrate

Trench-filling heteroepitaxy of germanium (Ge) on (001) silicon (Si) substrate is studied toward normal-incidence/free-space NIR photodetectors, where micron-thick Ge is prepared with a large surface coverage and in a growth time as short as possible. Arrayed trenches as deep as 1 μm are patterned on (001) Si in the [100] direction, intentionally deviating from the ordinary [110] direction. The molecular flux regime of CVD induces a substantial lateral growth of Ge at the trench sidewalls of the {010} planes, crystallographically identical to the (001) plane at the trench bottom. Despite the Ge thickness of 0.5 μm on an unpatterned surface, the 0.6 μm wide arrayed trenches of 1.0 μm in depth are successfully filled with Ge, although the filling is suppressed when increasing the trench width. The inter-trench Si fin width is also an important parameter concerning not only the surface coverage but also the structural degradation during the growth.

A Novel SiC Trench MOSFET with Self-Aligned N-Type Ion Implantation Technique.

We propose a novel silicon carbide (SiC) self-aligned N-type ion implanted trench MOSFET (NITMOS) device. The maximum electric field in the gate oxide could be effectively reduced to below 3 MV/cm with the introduction of the P-epi layer below the trench. The P-epi layer is partially counter-doped by a self-aligned N-type ion implantation process, resulting in a relatively low specific on-resistance (Ron,sp). The lateral spacing between the trench sidewall and N-implanted region (Wsp) plays a crucial role in determining the performance of the SiC NITMOS device, which is comprehensively studied through the numerical simulation. With the Wsp increasing, the SiC NITMOS device demonstrates a better short-circuit capability owing to the reduced saturation current. The gate-to-drain capacitance (Cgd) and gate-to-drain charge (Qgd) are also investigated. It is observed that both Cgd and Qgd decrease as the Wsp increases, owing to the enhanced screen effect. Compared to the SiC double-trench MOSFET device, the optimal SiC NITMOS device exhibits a 79% reduction in Cgd, a 38% decrease in Qgd, and a 41% reduction in Qgd × Ron,sp. A higher switching speed and a lower switching loss can be achieved using the proposed structure.

Ion Trajectory Control in Processing Plasmas for Nano-Fabrication

To realize ion trajectory control in processing plasmas for nano-fabrication, we applied amplitude modulation (AM) discharges to control of ion trajectory in high aspect trenches. We investigated behavior of incident ions in AR25 (aspect ratio = 25) trench structure in AM discharges using data of Ar+ ion with ion energy and ion angular distribution functions (IEDF and IADF) on the substrate obtained by the PIC-MCC model. AM discharges have higher ion flux onto the trench sidewalls than the continuous waveform (CW) discharges, whereas AM discharges have almost the same ion energy as CW ones. SRIM simulation results suggest that AM discharges can desorb more hydrogen atoms from TEOS-PECVD SiO2 films on the trench sidewall than CW ones, which explains the previous results of improved SiO2 film quality on trench sidewall by AM discharges.

Impact of Trap States at Deep Trench Sidewalls on the Responsivity of Island Photodiodes

Impact of Trap States at Deep Trench Sidewalls on the Responsivity of Island Photodiodes

Exploring oxide-nitride-oxide scalloping behavior with small gap structure and chemical analysis after fluorocarbon or hydrofluorocarbon plasma processing

The scalloping of oxide-nitride-oxide (ONO) stacked layers on vertical sidewalls during high-aspect-ratio contact etch is commonly seen and characterized by the horizontal etching of oxide and nitride layers at different etch rates. To understand the mechanisms of ONO scalloping in complex plasma chemistry, it is crucial to examine the surface chemistry of silicon dioxide and silicon nitride processed with single fluorocarbon (FC) or hydrofluorocarbon (HFC) gases. To simulate the isotropic etching of SiO2 and Si3N4 sidewalls, we use a horizontal trench structure to study the effect of neutral radicals produced by FC (Ar/C4F8), HFC (Ar/CH3F, CH2F2, or CH3F), FC/HFC (Ar/C4F8/CH2F2), or FC/H2 (Ar/C4F8/H2), plasma for aspect-ratio (AR) up to 25. To eliminate the effect of ions, oxide and nitride trench structures were treated by inductively coupled plasma. The changes in the film thickness as a function of AR were probed by ellipsometry. Additionally, x-ray photoelectron spectroscopy (XPS) measurements on oxide and nitride substrates processed by Ar/C4F8 and Ar/CH2F2 plasma were performed at various locations: outside of the trench structure, near the trench entrance (AR = 4.3), and deeper in the trench (AR = 12.9). We find a variety of responses of the trench sidewalls including both FC deposition and spontaneous etching which reflect (1) the nature of the FC and HFC gases, (2) the nature of the surfaces being exposed, and (3) the position relative to the trench entrance. Overall, both the etching and deposition patterns varied systematically depending on the precursor gas. We found that the ONO scalloping at different ARs is plasma chemistry dependent. Oxide showed a binary sidewall profile, with either all deposition inside of the trench (with FC and FC/H2 processing) or etching (HFC and FC/HFC). Both profiles showed a steady attenuation of either the deposition or etching at higher AR. On the nitride substrate, etching was observed near the entrance for HFC precursors, and maximum net etching occurred at higher AR for high F:C ratio HFC precursors like CHF3. XPS measurements performed with Ar/C4F8 and Ar/CH2F2 treated surfaces showed that Ar/C4F8 overall deposited a fluorine-rich film outside and inside of the trench, while Ar/CH2F2 mostly deposited a cross-linked film (except near the trench entrance) with an especially thin graphitic-like film deep inside the trench.

Enhancing the specific capacitance of a porous silicon-based capacitor by embedding graphene combined with three-dimensional electrochemical etching

A porous silicon-based capacitive structure with high specific capacitance is fabricated by three-dimensional electrochemical etching. As well as conventional planar electrochemical etching in two dimensions on the surface of a silicon chip, the lateral side walls of trenches engraved by a laser beam are also etched (third dimension). Platinum is deposited on both sides of the porous silicon film to create a capacitive structure that allows for stable measurement of the equivalent permittivity and specific capacitance of the trench-structured, layered porous silicon material. To eliminate the large parasitic effect due to the high roughness and air gaps between the metal layer and the porous silicon layer, nano-scale graphene is embedded into the surface pores of the porous silicon to enable good contact. After preliminary experiments, an etching approach based on a continuously decreasing current is adopted to obtain a strong porous silicon structure with long silicon pillars. Various laser engraving patterns were compared to determine the effect of three-dimensional etching. The results show that the increase in specific capacitance due to the laser trenches is positively correlated with the extent of lateral etching. The proposed method is suitable for improving the equivalent permittivity of the porous silicon layer without changing the device geometry or electrochemical etching parameters, and is also compatible with Si-VLSI technology.

Sidewall Modification Process for Trench Silicon Power Devices

In this study, trench sidewall modification processes were designed to improve profile uniformity and thereby enhance the electrical performance of silicon power devices in large-scale production. The effects of trench sidewall modification on the morphology, structure and electrical properties were studied. Plasma-induced damage in etching processes was also observed and briefly explained. Straight and smooth sidewall profiles were achieved through adjusting the SF6/CHF3 proportion in a combined etchant gas flow in the main etching procedure. By comparing HRSEM images from different etching protocols, it was evident that an enhanced CHF3 flow formed a proper passivation of the sidewall, eliminating the ion damages that are common in current main etch steps. To address the impurities introduced from the etchant gas and improve the gate oxide uniformity, further steps of depolymerization were applied in a plasma asher chamber, followed by wet clean steps. In the meantime, the plasma-induced charge accumulation effect was reduced by UV curing. Improved trench sidewall profiles and the gate oxide uniformity contributed to a lower leakage current between the gate and source terminals, leading to an overall yield enhancement of device properties in large-scale silicon wafer fabrication.

Normally-off operation in vertical diamond MOSFETs using an oxidized Si-terminated diamond channel

We fabricated (001) vertical diamond metal-oxide-semiconductor field-effect transistors (MOSFETs) with oxidized Si-terminated (C–Si–O) diamond channels on the surfaces and trench sidewalls. The C–Si–O diamond surface is approximately 1.0 eV weaker in negative electron affinity than the hydrogen-terminated (C–H) diamond surface, resulting in a smaller valence band bending between the interface of C–Si–O diamond surface and Al2O3, and larger the difference between the energy values of the fermi level and the valence band on the top (EF−EV), and the threshold voltage (Vth) shifts in the negative direction. As a result, the maximum drain current density was 108 mA/mm, the Vth was −9.0 V. Compared with conventional vertical diamond FETs using a C–H channel, the Vth was shifted more than 20 V in the negative direction to reach normally-off mode. The normally-off operation was achieved while maintaining high current density, which is the first case of normally-off operation that has been observed in vertical diamond FETs. In, addition, it was confirmed that the diode functions as a freewheeling diode by adding a reverse drain voltage and allowing current to flow, and the change of current-voltage characteristics was also investigated by swapping the source and drain positions and performing measurements.

Inductively Coupled Plasma Dry Etching of Silicon Deep Trenches with Extremely Vertical Smooth Sidewalls Used in Micro-Optical Gyroscopes

Micro-optical gyroscopes (MOGs) place a range of components of the fiber-optic gyroscope (FOG) onto a silicon substrate, enabling miniaturization, low cost, and batch processing. MOGs require high-precision waveguide trenches fabricated on silicon instead of the ultra-long interference ring of conventional F OGs. In our study, the Bosch process, pseudo-Bosch process, and cryogenic etching process were investigated to fabricate silicon deep trenches with vertical and smooth sidewalls. Different process parameters and mask layer materials were explored for their effect on etching. The effect of charges in the Al mask layer was found to cause undercut below the mask, which can be suppressed by selecting proper mask materials such as SiO2. Finally, ultra-long spiral trenches with a depth of 18.1 μm, a verticality of 89.23°, and an average roughness of trench sidewalls less than 3 nm were obtained using a cryogenic process at −100 °C.

Method for Keyhole-Free High-Aspect-Ratio Trench Refill by LPCVD.

In micro-machined micro-electromechanical systems (MEMS), refilled high-aspect-ratio trench structures are used for different applications. However, these trenches often show keyholes, which have an impact on the performance of the devices. In this paper, explanations are given on keyhole formation, and a method is presented for etching positively-tapered high-aspect ratio trenches with an optimised trench entrance to prevent keyhole formation. The trench etch is performed by a two-step Bosch-based process, in which the cycle time, platen power, and process pressure during the etch step of the Bosch cycle are studied to adjust the dimensions of the scallops and their location in the trench sidewall, which control the taper of the trench sidewall. It is demonstrated that the amount of chemical flux, being adjusted by the cycle time of the etch step in the Bosch cycle, relates the scallop height to the sidewall profile angle. The required positive tapering of 88° to 89° for a keyhole-free structure after a trench refill by low-pressure chemical vapour deposition is achieved by lowering the time of the etch step.

Study on the Transformation of Si Trench Profile With Low Pressure of SF₆/O₂ Containing Plasmas

The reason for the change of trench sidewall profile under low pressure of SF6/O2 containing plasma was explored by studying the trench morphology under different etching conditions. The result shows that the Si undercut decreases with the decreasing of pressure and the uniformity will become better. However, the sidewall of the trench presents a negatively tapered under low pressure. The reasons for different profile of trench are explored by the thickness of sidewall protective layer for the first time. The TEM results show that the trench sidewall forms a protective film with a thickness of about 100Å. The thickness of the oxide layer decreases from top to bottom. And the EDX results show that the main elements of the protective film are Si and O. Due to the decrease of oxide thickness, the width of trench bottom will become larger and larger, resulting in negatively tapered morphology. It is worth noting that the profile of trench changes to positively tapered again under the condition of low ratio of SF6/O2. Based on this, an optimized trench etching process is proposed and the etch rate is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.15{\mu }\text{m}$ </tex-math></inline-formula> /min and the selectivity to the oxide mask is 14.

Film Effectiveness Downstream the Trenches with Tilted Target Wall

Film cooling is a commonly-accepted effective way to protect the gas turbine hot sections from the high temperature products of the combustion chamber. Numerous film hole geometries have been the subject of investigation by many researchers over the past three decades with the aim of keeping the target wall under the maximum allowable temperature with the least amount of precious cooling air and minimum aerodynamic losses. In this study, we are proposing a new trench geometry that is fed by 30°-inclined embedded circular film holes entering from the trench sidewall. The cooling jets impinge on the opposite wall of the trench which is tilted towards the jets and then is pushed over the coverage wall by the main flow. Three trench geometries with the same exit area and tilt angles (the angle between the trench side- and top-wall) of 75°, 90°, and 105° degrees are tested for three blowing ratios of 0.5, 0.75, and 1.0, and the film effectiveness results are compared using the adiabatic pressure sensitive paint technique. CFD analyses are also performed using the realizable <math xmlns="http://www.w3.org/1998/Math/MathML" id="M1"> <mi>k</mi> <mo>−</mo> <mi>ε</mi> </math> turbulence model with the enhanced wall function option. Major conclusions of this study were that the trench geometry with the trench tilt angle of 75°, corresponding to the smallest trench volume, had the best performance at the lowest blowing ratio, and good agreement was observed between the CFD and test results.

Adhesion Strength of Amorphous Carbon Films Deposited on a Trench Sidewall

Hydrogenated amorphous carbon (a-C:H) films were deposited on the sidewall of 3-mm-wide stainless steel or Si trench, and the adhesion strength of the films was evaluated using a micro-scratch tester. Particularly, the effects of carbon ion implantation and Si-containing interlayer (a-SiCx:H) as the pretreatments on the adhesion strength of the a-C:H films prepared on the trench sidewall were investigated. It was found that both carbon ion implantation and interlayer improved the adhesion strength of the a-C:H films deposited on the trench sidewalls. In addition, the carbon ion implantation dominated the adhesion strength of the a-C:H films for the Si substrates, and the interlayer for the stainless steel substrates. In the case of the stainless steel substrates, the carbon was accumulated on the surface of the trench sidewall instead of implantation, whereas the carbon ions were implanted to the Si substrates on the trench sidewall to form a mixing layer. The a-SiCx:H interlayer forms Fe–Si bonds between the stainless steel substrate and the interlayer, which is thought to improve the adhesion strength. It was also found that there is a negative correlation between the trench depth and the adhesion strength regardless of the pretreatment methods.

Study of Vertical Capacitance in an n-Type 4H-SiC Stepped Thick-Oxide Trench MOS Structure

In this work, characteristics of trench sidewall capacitance were investigated in a 4H-SiC stepped thick-oxide (STO) trench metal–oxide–semiconductor (MOS) structure. Multigroup SiC trench MOS capacitor test patterns with different structures and geometric parameters were designed and fabricated. From the capacitance–voltage measurements, the characteristics of the described SiC STO trench MOS were calculated and analyzed, including the thicknesses of the oxide at different locations in trench, the position of the oxide step at trench sidewall, and the flat-band voltages as well as the oxide charge densities of MOS from the upper part and lower part of oxide step at trench sidewall. Results showed that the flat-band voltages of MOS from the upper part (10.2 V) and lower part (12.5 V) of trench sidewall step had pronounced positive shifts over the ideal flat-band voltage (0.36 V), indicating a massive negative charges in the sidewall oxide film. Meanwhile, the net oxide charge density of MOS from the lower part of sidewall step ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 0.92\times10$ </tex-math></inline-formula> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-2}$ </tex-math></inline-formula> ) was smaller than that from the upper part ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 2.41\times10$ </tex-math></inline-formula> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-2}$ </tex-math></inline-formula> ), which was likely attributed to the massive shallow states in the oxide and to the poor quality of the thick-oxide film grown via chemical vapor deposition technology. The present works are providing a convenient technology to monitor the trench MOS structure by measuring the capacitance during SiC trench MOSFETs fabrication.

Novel Backside Structure for Reverse Conducting Insulated-Gate Bipolar Transistor With Two Different Collector Trench

A novel reverse-conducting insulated gate bipolar transistor (RC-IGBT) with two different collector trench (DCT) is proposed. One of the collector trenches is filled with heavily doped N-type polysilicon (N-poly) and the other is filled with heavily doped N- and P-poly. An electron accumulation layer is formed along the sidewall of trench owing to built-in potential difference between the N-poly and the N-drift region. The electron accumulation layer and collector trenches block the electric field, which behaves just like the N-buffer layer of the conventional RC-IGBT (Con. RC-IGBT). Similarly, due to potential difference between the P-poly and N-drift region, a high-density hole inversion layer is formed to narrow the electron current path as a high resistance. The DCT RC-IGBT achieves snapback-free in a small cell pitch without additional control. Moreover, the DCT RC-IGBT shows better tradeoff between turn-off loss and ON-state voltage drop than that of con. RC-IGBT. For the same forward voltage drop, the turn-off loss is reduced by 26%.