Translinear Principle Research Articles

BJT Based Translinear Implementation of an Evolutionary Optimised Non-Linear Function for Sensor Linearisation

The linear characteristics of temperature sensors are affected by material properties, aging, self-heating, lead resistance, and external interference. This study aims to improve sensor characteristics by overcoming power consumption and response time limitations. An evolutionary optimised log-ratiometric function is implemented for sensor linearisation using a translinear circuit. The differential evolution optimisation strategy is used to find the optimum values of the linearising parameters in the non-linear function. Further, these parameters are applied to the current mode circuit to linearise the selected sensors as an input current source. Due to higher fidelity, better comprehensive dynamic range, and improved linear areas, implementing the non-linear function using the BJT-based current mode circuit results in a better full-scale error reduction capability than MOSFET-based translinear implementation. Furthermore, the devices such as Gallium Arsenide Field-Effect Transistors (GaAsFET) and Modulation-Doped FET (MODFET) could be used in place of BJT in the future for additional error reduction due to rapid response speed, low power consumption, and reduced internal noise. Thus, the translinear implementation of the non-linear function can enhance the sensor characteristics in all aspects.

Enhancing sensor linearity through the translinear circuit implementation of piecewise and neural network models

<abstract><p>The performance of the control system relies on the linearity of the sensor, which can be influenced by various factors such as aging and alterations in material properties. However, current sensor linearization techniques, such as utilizing neural networks and piecewise regression models in the digital domain, suffer from issues like errors, excessive power consumption, and slow response times. To address these constraints, this investigation employs a translinear based analog circuit to realize neural networks and piecewise regression models for the purpose of linearizing the selected sensors. A conventional feed-forward back propagation network is constructed and trained using the Levenberg-Marquardt algorithm. The developed linearization algorithm is implemented using a translinear circuit, where the trained weights, biases, and sensor output are fed as input current sources into the current-mode circuit. Further in this work, the piecewise regression model is designed and implemented using a translinear circuit and the breakpoint is determined using 'R' language. The simulation results indicate that the implementation of the current-mode circuit with metal-oxide-semiconductor field-effect transistors (MOSFETs) for the neural network algorithm leads to a substantial reduction in full-scale error as compared to the piecewise current mode model. Additionally, a performance analysis was conducted to compare the utilization of current-mode circuits with digital approaches for the linearization of sensors. The proposed translinear implementation surpasses the other researcher's work by delivering notable results. It showcases a significant improvement in linearity, ranging from 60% to 80%, for the selected sensors. Furthermore, the proposed implementation excels not only in linearity but also in terms of both response speed and power consumption. The improvement in the linearity of the sensor can be enhanced further by replacing the MOSFETs with bipolar transistors or any versatile materials such as gallium arsenide or gallium nitride-based transistors.</p></abstract>

Design of Current-Mode versatile Multi-Input analog multiplier topology

In this paper, a novel n-input 2n orthant class-AB current-mode multiplier topology is presented. The proposed analog current-mode multiplier is implemented by using two basic blocks, which are a current splitter and a one-quad multiplier. These blocks are based on the translinear circuit principle. Moreover, the designed multiplier can be easily extended for multi-input structures. Many different scenarios presenting particular usage of the proposed multiplier structure are presented as well. The functionality of all the proposed circuits utilized in different cases is verified by using the PSpice simulation program, where 0.13 μm IBM CMOS technology parameters are employed. The simulation results show that 0.225 mW power consumption and under 3 % Total Harmonic Distortion are observed for the two-input circuit. Furthermore, the bandwidth and the dynamic range of the proposed circuit for the three-input circuit are 165 MHz and 29.54 dB, respectively.

1 V, 20 nW True RMS to DC Converter based on Third Order Dynamic Translinear Loop

This paper presents a novel current-mode true RMS–DC converter based on the dynamic translinear principle. The converter is designed using a third-order translinear loop, resulting in a very compact and simple circuit. The proposed circuit is designed in 65 nm CMOS technology, operates with 1 V power supply, has only 14 transistors and performs satisfactorily over a wide input current range of 300 nA–950 nA and for a frequency range of 600 Hz–650 kHz for a capacitance value of 10 nF. The frequency range of operation can be tuned by varying the external off chip capacitor and the bias current. The circuit consumes 20 nW static power, 1.6 μW maximum dynamic power and offers the lowest FOM among the other RMS–DC converter circuits presented in the literature. Comprehensive mathematical analysis along with the post layout simulation results confirm the validity of the proposed circuit. To test the use of converter in real world scenarios, the proposed converter is introduced within a typical ECG detection system and the results show that the circuit is an attractive solution for RMS–DC conversion in low-voltage low-power applications.

A translinear principle based low-power high-precision RMS-to-DC converter in CMOS technology

A translinear principle based low-power high-precision RMS-to-DC converter in CMOS technology

Analog Gaussian Function Circuit: Architectures, Operating Principles and Applications

This review paper explores existing architectures, operating principles, performance metrics and applications of analog Gaussian function circuits. Architectures based on the translinear principle, the bulk-controlled approach, the floating gate approach, the use of multiple differential pairs, compositions of different fundamental blocks and others are considered. Applications involving analog implementations of Machine Learning algorithms, neuromorphic circuits, smart sensor systems and fuzzy/neuro-fuzzy systems are discussed, focusing on the role of the Gaussian function circuit. Finally, a general discussion and concluding remarks are provided.

Synthesis and study of evolutionary optimised sensor linearisation with translinear & FPGA circuits

ABSTRACT Linear response characteristics of sensors are affected by ageing and changes in material properties. However, existing methods for improving these characteristics are disadvantaged by recurrent full-scale errors and insufficient speed. Accordingly, this study aims to reduce temperature sensor non-linearity through implementation of evolutionary optimised non-linear functions via a translinear-based application-specific integrated circuit. Moreover, the translinear-based analogue computation method is compared to a proposed field programmable gate array (FPGA)-based digital computation methodology to develop an alternative method for linearisation at sensor nodes (edge computing). The optimal values of the linearisation parameters for selected thermocouples are determined using the covariance matrix adaptation evolutionary strategy. Specifically, these optimal values are input in order to realise the non-linear functions. Experimental results reveal that FPGA offers a lower full-scale error than that of the translinear-based computation, although the translinear method can accomplish the required linearisation with fewer components (e.g. Data Converters), less delay and less power. Further, analogue computation through the proposed single chip-based method can utilise the latest processes, e.g. gallium nitride or pseudomorphic high electron mobility, for an enhanced error reduction. The comparative result shows that the translinear method with recommended processes can correct the non-linearity of sensors in all aspects.

A Novel Pseudo-Taylor-Exponential Approximation Technique for Input–Output Range Extension with Reduced Linearity Error and its Current-Mode CMOS Implementation

A novel mathematical approach has been proposed for input–output range extension of Pseudo-Taylor-Exponential-Approximation (PTEA) for achieving over seven-decade exponential function, while reducing the linearity error by 1 dB and attaining simple coefficients such as to realize this technique in designing the MOSFET based circuit. This new MPTEA technique, has been successfully utilized for its current-mode (I-I) CMOS implementation involving translinear principle of MOSFETs in weak inversion (WI) region. The CMOS synthesis procedure has been detailed and relevant second-order effects consists of noise, bulk-effect etc. have been explored. For post-layout simulations of the synthesized CMOS implementation, the SPECTRE simulation tool from Cadence, with 180 nM CMOS parameters, has been utilized to justify its practical workability. The proposition, in its CMOS layout, occupies an area of 0.0126mm2 only. It consumes only ≈4.92 μW static power by utilizing ± 0.65 V power supply and produces 146.5 dB range of linear-in-dB output with ± 1 dB linearity error.

A New Extremely Low Power Temperature Insensitive Electronically Tunable VCII-Based Grounded Capacitance Multiplier

In this brief, a new circuit topology to realize an electronically tunable grounded capacitor multiplier with extremely low power consumption and low supply voltage requirement is investigated. The proposed circuit uses an electronically tunable second generation voltage conveyor (VCII) and a single floating capacitor. Owing to the translinear principle, current gain of VCII is varied through a control current and, as a result, the value of simulated capacitor is also varied. Favorably the obtained gain is temperature insensitive. Both of the required supply voltage and control currents are very low because all transistors are biased in subthreshold region: therefore, electronic tunability is achieved while the power consumption is kept at very low value. In addition, the circuit realization is very simple since only twelve transistors are required. Simulation results, performed at schematic level in 0.18 $\mu \text{m}$ CMOS technology and supply voltage of ±0.3V, are presented. It is shown that a multiplication factor from 1 to 100 is possible while the power consumption varies from 10 nW to 67 nW.

A novel square wave generator based on the translinear circuit scheme of second generation current controlled current conveyor-CCCII

A robust square wave generator employing a sole capacitor and two resistors has been presented in this study. Low power as well as popular translinear circuit scheme of Second generation current controlled current conveyor-CCCII has been taken as an active element to implement the proposed square wave generator. CCCII inhibits promising features like availability of three mutually independently and electronically adjustable parameters corresponding transconductance (gm), intrinsic resistance (r) of the current input terminal and current gain between two terminals) that are very prevalent for control applications accepted currently. The operating frequency of the proposed model has been analyzed with respect to the passive components present there, with no exposure of output signals to the thermal voltage (VT). Electrical/Device properties (like Noise, Threshold, area etc.) of the proposed circuit have also been discussed in this work. The simulation work was carried out on Synopsis Hspice tool (v-2008.03) from Avant. Satisfying results with anticipation of theoretical and simulated results, including precision (consistency assessment) with Pareto analysis (Ist order Best Test flavored by Decision making analysis) were observed during the study. The 45 nm BSIM CMOS modelling parameters were adopted to prove the theory. The elementary purpose of using such parameters is to maximize the circuit drive and lowering the leakage current. Another purpose of using these modelling parameters is to enhance the realization of the proposed circuit in the form of chip die and further get it fabricated in custom Integrated circuit(IC) form, from a Standard local foundry. Maximum power consumption of the circuit is 600 µW, with ± 1 V rail to rail operating voltages.

Analog Multiplier Based on Squarer Cells

In this paper, a current-mode analog multiplier circuit is proposed that utilizes MOS translinear principle. The parameters of TSMC 0.18µm technology are used to design the proposed multiplier that employs CMOS transistors operating in weak inversion region. Simulations are performed by HSPICE for the circuit to prove its great merits of; low power consumption (100µW), low supply voltage (1.6V), body effect immunity, wide input range (±100nA), bandwidth of 1 MHz, and THD of 4%.

Comparative Study of Trans-linear and Trans-impedance Readout Circuits for Optical Beam Deflection Sensors in Atomic Force Microscopy

The optical beam deflection sensor remains the most popular force detection method used in atomic force microscopy. With the recent development of short cantilevers, a means for measuring small deflections at high frequencies has become a challenge. Minimizing the noise level of the readout electronics without significantly limiting the detection bandwidth still remains a challenge. In this work, a recently proposed trans-linear readout circuit-based technique, in which necessary analog arithmetics are done in the current domain instead of the voltage domain, is compared to a more traditional trans-impedance readout circuit-based topology. Our developed trans-impedance readout circuit recorded a noise floor of 9.48 × 10−13 V2 Hz−1 compared to 1.41 × 10−11 V2 Hz−1 for the trans-linear readout circuit. Also, the measured −3 dB bandwidth of 11 MHz for the transimpedance readout circuit was slightly higher than the 10 MHz for the trans-linear readout circuit. Trans-impedance readout circuits, with proper circuit design considerations and careful selection of electronic parts, still remain competitive for use in high-speed operations in atomic force microscopy.

A 213-nW/Channel Analog Euclidian Vector Normalizer

This brief presents a novel low-power analog Euclidian vector normalizer for analog signal processing in vector forms, such as the preprocessing of sensor array signals. Instead of using multiple stages of translinear circuits to synthesize the Euclidian norm with square root, squared sum, and division functions, this circuit performs concurrent Euclidian vector normalization on input signals with a feedback control loop to achieve a compact area and low power consumption. A simple two-step calibration is also provided to overcome device mismatches. This 6-channel normalizer is part of an analog gas sensing front end and was implemented in a 65-nm low-power CMOS technology with an area of 0.053 mm2. It consumes a maximum current of $2.08~{\mu }\text{A}$ from 0.6/0.65-V supplies with a response time of 6.5 ${\mu }\text{s}$ , thus achieving a low energy per operation of 1.39 pJ/channel.

On the realisation of current-mode four-quadrant CMOS cuber

For the first time, a fully current-mode CMOS cube-law generator (cuber) that gives output in four quadrants is presented. The proposed circuit design is based on translinear principle of MOSFETs operating in weak inversion region. The details on circuit synthesis have been given and the second-order effects on the performance of the cuber have also been considered in this communication. Validation by post-layout simulation have been carried out on Virtuoso-SPECTRE tool with 180 nm GPDK CMOS process parameters. It has been found that using ± 0.5 V supply voltage, the realized current mode cuber circuit works for an input range of ± 200 nA (± 8 normalized input range) while consuming only 139.9 nW static power and contributes a maximum of ± 1.5 dB error over a wide input range of ± 25 nA to ± 200 nA in all four-quadrants.

CMOS design of computational current-mode static and dynamic functions based on analog translinear cell

In this paper, the systematic realizations of some low-power nonlinear current-mode computational/configurable analog blocks (CABs) are presented. These CABs are based on a most demanded novel precise analysis and removal method of complete non-idealities of CMOS transistors. The proposed CAB architecture consists of a novel MOS translinear cell (MTC) that includes two overlapping up-down loops using MOS translinear principle (MTLP) in sub-threshold region. The proposed design with properly signal/bias injection scheme to MTC via NMOS-PMOS arrays is able to produce some current-mode nonlinear static and dynamic functions. Those are as vector summation, cube/third power, true RMS to DC converter and first-order low-pass log-domain filter. The designed functions are simulated by HSPICE simulator in TSMC 0.18 µm (level-49 parameters) CMOS technology. Pre and post-layout simulation results both plus Monte Carlo analysis are compared with other artworks that verified the functionality, flexibility and superiority of the proposed CABs.

Design of Squarer Circuit in Sub-threshold Mode

Historically, analog designs have been assumed as a voltage mode based signal processing. However, the necessity of high speed circuits operating at reduced supply voltage has lead to a development of new circuit topology referred as current-mode designs. For low power low voltage designs the applications using translinear principle based circuits has become an area of research and interest. It has wide application in nonlinear signal processing and to build basic active elements. Mode of MOS transistor used in analog circuit realization of is important parameter deciding the performance of the circuit. In this paper, a squarer circuit is proposed based on sub threshold-mode MOS transistors exhibiting the exponential current-voltage characteristic. The simulations have been performed on model files of TSMC 0.18 micrometer technology with the help of ELDO Simulator.

A four-quadrant current multiplier/divider cell with four transistors

We propose a four quadrant six transistor current multiplier cell based on the translinear principle. The cell is further modified by using resistive feedback to remove two PNP transistors hence re...

A new CMOS tunable floating capacitance multiplier

ABSTRACTThis paper presents a new tunable complementary metal oxide semiconductor (CMOS) floating capacitance multiplier. The multiplier uses the translinear principle with metal-oxide semiconductor field effect transistors operating in the sub-threshold region. The multiplication factor is tunable to meet the design requirements. The Tanner T-spice simulator confirms the functionality of the design using 0.18-µm CMOS Technology. The circuit operates from a supply voltage of ±0.75 V and the capacitance can be magnified 300-fold.

A New CMOS Controllable Impedance Multiplier with Large Multiplication Factor

This paper presents a new compact controllable impedance multiplier using CMOS technology. The design is based on the use of the translinear principle using MOSFETs in subthreshold region. The value of the impedance will be controlled using the bias currents only. The impedance can be scaled up and down as required. The functionality of the proposed design was confirmed by simulation using BSIM3V3 MOS model in Tanner Tspice 0.18 μm TSMC CMOS process technology. Simulation results indicate that the proposed design is functioning properly with a tunable multiplication factor from 0.1- to 100-fold. Applications of the proposed multiplier in the design of low pass and high pass filters are also included.

A Novel Exponential Approximation with $$\pm 0.21\,\hbox {dB}$$ ± 0.21 dB Error for Realizing an Improved CMOS Exponential Function Generator

A new modified pseudo-Taylor exponential approximation is presented for realizing a current-to-current exponential function generator. The proposed approximation for exponential function generation has been implemented using translinear principle of MOSFETs operating in weak inversion region. The SPECTRE simulation tool from Cadence, with 180 nM CMOS process parameters, has been utilized for testing the workability of the CMOS implementation of the proposed approximation, which uses only $$\pm 0.5\hbox {V}$$±0.5V power supply. The post-layout simulation results of the proposed CMOS exponential generator, thus, consume only $${\approx }119\,\hbox {nW}$$ź119nW power and produce 51.6 dB range of linear-in-dB output with only $$\pm 0.21\,\hbox {dB}$$±0.21dB error while occupying an area of $$0.26\,\upmu \hbox {m}^{2}$$0.26μm2.