Transition Delay Fault Coverage Research Articles

A new circuit for at-speed scan SoC testing

It is very important to detect transition-delay faults and stuck-at faults in system on chip (SoC) under 90 nm processing technology, and the transition-delay faults can only be detected by using an at-speed testing method. In this paper, an on-chip clock (OCC) controller with a bypass function based on an internal phase-locked loop is designed to test faults in SoC. Furthermore, a clock chain logic which can eliminate the metastable state is realized to generate an enable signal for the OCC controller, and then, the test pattern is generated by automatic test pattern generation (ATPG) tools. Next, the scan test pattern is simulated by using the Synopsys tool and the correctness of the design is verified. The result shows that the design of an at-speed scan test in this paper is highly efficient for detecting timing-related defects. Finally, the 89.29% transition-delay fault coverage and the 94.50% stuck-at fault coverage are achieved, and it is successfully applied to an integrated circuit design.

Flip–flop selection for partial enhance scan chain using DTESFF for high transition delay fault coverage

In nanometric technologies, testing of delay faults in the integrated circuits is becoming mandatory during manufacturing test. Delay fault testing involves two test vectors. Scan based designs is used for delay fault testing with architectural limitations of traditional scan limits the two pattern delay tests that can be applied to a design which results in degraded delay test coverage. Transition delay fault (TDF) coverage improves appreciably by the use of enhanced scan design as it solves the problem by supporting arbitrary delay test vector pairs at the cost of high area overhead. It also needs fast hold signal which is analogous to scan enable signal as in case of LOS testing. Delay testable enhanced scan flip–flop (DTESFF) has been proposed as a low cost DFT technique to achieve high TDF coverage using enhanced scan design without the need of fast hold signal. In this work, a partial DTESFF scheme augments few scan flip–flops with the DTESFF design by choosing scan flip–flops carefully. It attains most of the TDF coverage advantages of a full DTESFF design with reduced area overhead. Significant improvement in TDF coverage for partial enhance scan using DTESFF has been seen on ISCAS’ 89 benchmark circuits.

Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume

We propose a flip-flop selection method to reduce the overall volume of transition delay test data, by replacing a small number of selected regular scan cells with enhanced scan cells. Relative measures are presented to reflect the gains when controlling a scan cell to a certain value, and guide the scan cell selection. Experimental results on larger IWLS 2005 benchmark circuits show that, to achieve the same fault coverage of the pure launch on capture (LOC) approach, the volume of test data can be reduced to a half on average by replacing only 1% of regular scan cells to enhanced scan cells. The transition delay fault coverage can also be improved using the proposed method with equally low area overhead.

Performance evaluation of delay testable enhanced scan flip-flop

Delay faults are regularly encountered in nanometric regime that’s why it is very important to detect these faults during the manufacturing test. Testing of delay fault requires two test vectors. In general delay faults are tested using scan-based designs. The second test vector is generated in scan either by broadside test (launch of capture test) or by skewed load test (launch-on-shift). Broadside test is preferred over skewed load test approach in designs because it is implemented by system clock for scan operations while skewed load delay test requires fast scan enable signal which is not supported by most of designs but skewed load delay test provides better transition delay fault coverage with fewer test patterns compared to broadside delay test. For maximum detection of delay faults it is essential that vectors in the pair should be independent. Due to structural limitation of scan independent test vector can’t be applied to the design, which results in degradation of delay test coverage. However this can be accomplished by the use of enhance scan flip-flop which presents the application of independent delay test vector pair at the cost of high area overhead and also requires fast hold signal, similar to scan enable signal in case of skewed load testing. This paper presents a new enhanced scan flip-flop design implemented with slow hold signal and we also discussed the performance penalty caused by the delay testable enhance scan flip-flop. Experimental results shows improvement in transition delay fault coverage on ISCAS 89 benchmark circuit with this method.

Test Generation in Systolic Architecture for Multiplication Over $GF(2 ^{m})$

This paper presents a test generation technique for detecting stuck-at (SAF) and transition delay fault (TDF) at gate level in the finite-field systolic multiplier over GF(2m) based on polynomial basis. The proposed technique derives test vectors from the cell expressions of systolic multipliers without any requirement of Automatic test Pattern Generation (ATPG) tool. The complete systolic architecture is C-testable for SAF and TDF with only six constant tests. The test vectors are independent of the multiplier size. The test set provides 100% single SAF and TDF coverage.

Simplified bit parallel systolic multipliers for special class of Galois field (2m) with testability

This study presents a simplified structure of bit parallel systolic multiplier over Galois fields (GFs) over the set GF(2m) suitable for cryptographic hardware implementation. A redundant standard basis representation with the irreducible all one polynomial is considered. The systolic multiplier consists of (m+1)2 identical cells, each consisting of one two-input AND gate, one two-input XOR gate and two one-bit latches. This architecture is well suited to very large-scale integration implementation because of its regularity modular structure and unidirectional data flow. The proposed multipliers have clock cycle latency of (m+1). This architecture has a total reduction of m2 D-flip-flops compared to earlier bit parallel systolic multiplication architecture. As the finite-field multiplier is one of the complex blocks in cryptographic hardware and need secure testability to avoid unwanted access into the on-chip security blocks, the authors also introduce an on-chip testing scheme. The authors propose a test generation technique for detecting stuck-at fault (SAF), transition delay fault (TDF), stuck-open fault (SOF) and path delay faults (PDFs) at the gate and cell level in the systolic architecture. The authors also show that realistic sequential cell fault can be detected only by 12 single input change test vectors in the complete systolic multiplier over GF(2m). The proposed technique derives test vectors from the cell expressions of systolic multipliers without any requirement of an automatic test pattern generation tool. The complete systolic architecture is C-testable for SAF, TDF, SOF and PDF with only 12 constant tests. The test vectors are independent of the multiplier size. The test set provides 100% single SAF, TDF, SOF and PDF coverage.

Improved Launch for Higher TDF Coverage With Fewer Test Patterns

Due to the limitations of scan structure, the second vector in transition delay test is usually applied either by shift operation or by functional launch, which possibly results in unsatisfying transition delay fault (TDF) coverage. To overcome such a limitation for higher TDF coverage, a novel improved launch delay test technique that combines the pros of launch-on-shift and launch-on-capture tests is introduced in this paper. The proposed method can achieve near perfect TDF coverage with fewer test patterns without the need for a global fast scan enable signal. Experimental results on ISCAS89 and ITC99 benchmark circuits are included to show the effectiveness of the proposed method.

A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes

At-speed scan testing has become mandatory due to the extreme CMOS technology scaling. The two main at-speed scan testing schemes are namely Launch-Off-Shift (LOS) and Launch-Off-Capture (LOC). As it can be easily implemented, LOC has been widely investigated in the literature in the last few years, especially regarding test power consumption. Conversely, LOS has received much less attention. In this paper, we propose a comparison between the two testing schemes in terms of transition fault coverage and power consumption, in order to quantify the pros and cons of LOS with respect to LOC. This study shows that LOS exhibits higher performance in transition delay fault coverage and pattern count, and does not require a significant amount of extra power (with respect to LOC), especially in terms of peak power dissipation. These facts may represent convincing arguments for its wider use and development.

Scan cell design for launch-on-shift delay tests with slow scan enable

Most scan-based designs implement the scan enable as a slow speed global control signal, and can therefore only implement launch-on-capture (LOC) delay tests. Launch-on-shift (LOS) tests are generally more effective, achieving higher fault coverage with significantly fewer test vectors, but requiring a fast scan enable. A low cost solution for implementing LOS tests by adding a small amount of logic in each flip-flop to align the slow scan enable signal to the clock edge is presented. The new design is much more efficient when compared with other recent proposals and can support full LOS testing. It can be further modified for mixed LOC/ LOS tests that achieve transition delay fault coverage approaching 95% for the ISCAS89 benchmarks.

Enhancing delay fault coverage through low-power segmented scan

Reducing power dissipation during test has been an active area of academic and industrial research for the last few years and numerous low-power DFT techniques and test generation procedures have been proposed. Segmented scan has been shown to be an effective technique in addressing test power issues in industrial designs . To achieve higher shipped product quality, tests for delay faults are becoming essential components of manufacturing test. For the first time, it has been demonstrated that segmented scan facilitates increased delay fault coverage without degrading the reduction of the switching activity obtained by segmented scan. The increased transition delay fault coverage is achieved through careful selection of the capture cycle application. Experimental results on larger ISCAS-89 and ITC-99 benchmarks show that using three segments, on average, fault coverage using launch off capture can be increased by about 7.4% while simultaneously reducing the peak switching activity caused by capture cycles by over 20.4%.

Statistical estimation of delay fault detectabilities and fault grading

In this paper we present a technique to statistically estimate transition delay and path delay fault coverage. The basic method is an extension of STAFAN to include delay faults. By partitioning a combinational circuit into non-overlapping fanout free logic cones, we accurately calculate the transition sensitization controllabilities of 0 ⇀ 1 and 1 ⇀ 0 transitions of the lines within a fanout free logic cone to the output of the fanout free logic cone for each fanout free logic cone. A strategy to calculate the transition observabilities of fanout stems is proposed. The detectability of a path delay fault is evaluated as the product of the observabilities of the input line to its head gate within each fanout free logic cone on the path multiplied by the transition controllability of the path. When compared with the fault simulations, the estimations of transition delay fault coverage are within 2.3%. Also, the technique gives reasonably good path delay fault coverage estimation for large fault set of the ISCAS85 benchmark circuits.