Transistor Placement Algorithm Research Articles

BonnCell: Automatic Cell Layout in the 7-nm Era

Multipatterning technology used in 7-nm technology and beyond imposes more and more complex design rules on the layout of cells. The often nonlocal nature of these new design rules is a great challenge not only for human designers but also for existing algorithms. We present a new flow for automatic cell layout generation that is able to deal with these challenges by globally optimizing several design objectives simultaneously. Our transistor placement algorithm not only minimizes the total cell area but at the same time guarantees the routability of the cell and finds a best arrangement and folding of the transistors. Our routing engine computes a detailed routing of all nets simultaneously. It computes a netlength optimal routing using a mixed-integer programming formulation. Additional DFM constraints are added to this model to improve yield and reduce chip manufacturing costs. We present experimental results on current 7-nm designs. Our approach allows to compute optimized layouts within a few minutes, even for large complex cells. The algorithms are used for the design of logic cells compatible with a published 7-nm technology from a leading chip manufacturer where they meet manufacturability requirements and significantly reduced design turn around times.

Optimization-based placement algorithm for BiCMOS leaf cell generation

We present a transistor placement algorithm for the automatic layout synthesis of logic and interface cells comprised of a mixture of MOS and bipolar devices. Our algorithm is applicable to BiCMOS logic cells, ECL logic cells as well as TTL, CMOS and ECL compatible input/output (I/O) cells. The transistor placement problem is transformed into a layout floorplan design problem with a mixture of rigid and flexible modules. A constructive branch-and-bound algorithm is used to minimize the area of synthesized circuits subject to pre-placement constraints. Experimental results indicate that the algorithm can produce efficient placements under fixed-height constraints. The design space exploration mechanism can be controlled by the user so as to apportion computing resources judiciously. >

An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis

A layout style that enables either an automatic layout synthesizer or a layout designer to take full advantage of the second metal layer available from today's technology is proposed. The style not only facilitates power/ground diffusion overlapping but also simplifies the intracell routing problem by having power/ground in the middle and routing in the upper and the lower constraint-free regions. An automatic leaf cell layout synthesizer, called THEDA.P, that is based on the proposed style has been implement. Using the same transistor placement algorithm, THEDA.P outperforms a synthesizer based on T. Uehara and W.M. van Cleemput's (1981) approach by almost 20% in layout compactness across a wide range of small-scale integrated circuits. THEDA.P has been used to build a standard cell library that was previously handcrafted. Results from designing two modules show that THEDA.P's layout quality is very competitive. >

A transistor‐island growing algorithm in a CMOS cell pattern generation

AbstractA transistor placement algorithm which generates a placement from a circuit diagram is described and evaluation results are presented. This algorithm is not guaranteed to be optimum; however, it can generate efficient placements for a wide range of cells with an equal or an unequal number of PMOS and NMOS transistors. The basic idea is to divide a problem into four subproblems, each of which independently attempts to minimize the number of diffusion separations, to straighten the gate‐wirings between PMOS and NMOS transistors, to minimize the estimated total wiring length, and to minimize the trunk density by utilizing the logical structure of an input circuit diagram. This algorithm was applied to the cell library generation and also to some “difficult examples” suggested in other papers. The generated cell patterns can actually be used and are comparable to other results.