Transistor Level Netlist Research Articles

Efficient Circuit Structure Analysis for Automatic Behavioral Model Generation in Mixed-Signal System Simulation

For mixed-signal systems, identifying the analog and digital circuit blocks in the transistor-level netlist has many benefits for system analysis and verification. However, existing approaches still have difficulty handling large mixed-signal designs with millions of transistors, especially when multiple analog structure patterns are included. In this paper, we propose an efficient structure recognition methodology to support analyzing highly complex designs with various circuit structures and different devices. In order to tackle the complexity of real cases, a hierarchical partition-based analysis methodology and an encoding-based fast screening technique are proposed in this work. To correctly ascertain the boundary of analog and digital structures, we propose an enhanced direct current connection (DCC) partition method and combine it with the analog structure analysis flow. The non-transistor devices, such as resistors and capacitors, are also included in our recognition flow to improve the recognition capability and accuracy. As demonstrated with two industrial cases, the behavioral models generated from the structure recognition results do help to improve the efficiency of the AMS system verification.

FROSTY: A program for fast extraction of high-level structural representation from circuit description for industrial CMOS circuits

This paper presents FROSTY, a computer program for automatically extracting the high-level structural representation of a large-scale digital CMOS circuit from its transistor-level netlist and a library of subcircuit descriptions. To handle the complexity and diversity of industrial circuits, FROSTY combines traditional structural recognition and pattern matching methods into a two-step extraction process. First, logic structures based on channel-connected-components are recognized from a circuit netlist and from all library subcircuits, and are condensed into “macro devices” or called logic gates. This leads to hybrid netlists that contain the recognized logic gates and remaining transistors. Then annotated graphs representing the connectivity and properties of logic gates and remaining transistors are constructed. Compared to transistor-level netlists, these hybrid graphs are much smaller in size, more distinguishable in structure, and are thus more suitable for labeling-based pattern matching. An efficient pattern matching algorithm is then applied to extract the high-level structural representation from these condensed circuit graphs. FROSTY has demonstrated to be orders of magnitude faster than the pattern matching-based extraction program SubGemini, and can extract entire industrial designs with several hundreds of thousands of transistors in a few minutes on a modern Sun workstation. Furthermore, the FROSTY algorithm scales well with the size of a circuit.

Using robust adaptive mixing for statistical fault macromodelling

The design and analysis of analogue circuits can be speeded up if accurate macromodels are used in place of full, transistor-level netlists. Similarly, testability analysis of analogue circuits at the transistor level is difficult because of the large CPU times needed for fault simulation. Macromodelling circuits under catastrophic fault conditions is difficult because the faulty behaviour is not easily predicted. Moreover, the variances in faulty behaviour, because of parametric tolerances, are not the same as the variance of the fault free behaviour. An algorithm is presented for statistical fault macromodelling of analogue circuits. The circuit macros are modelled using a robust adaptive mixing algorithm, which is based on mutual information theory and robust statistical methods. The experimental results show that the CPU time required for statistical fault macromodelling is very small and the model accuracy is very high.

Symbolic behavioral model generation of nonlinear analog circuits

A new method for symbolic behavioral model generation of nonlinear analog circuits is presented. Equation-based simplification techniques for symbolic analysis of nonlinear circuits are proposed. They comprise global and local simplification operations which are performed on the system of nonlinear circuit equations. This system is derived from a transistor level netlist. Behavioral models are generated for DC-transfer and multiple AC operating conditions using an efficient error estimation algorithm. They include symbolic physical circuit parameters and allow deeper insight into nonlinear circuit behavior. Some examples are given to show the feasibility of this approach.

Excellerator: custom CMOS leaf cell layout generator

A description is given of a program, Excellerator, which automatically generates full-custom symbolic CMOS cell layouts. The input is a transistor-level netlist with optimal constraints on layout shape and I/O port positions. The output is a high-quality virtual-grid-based layout suitable for use in a two-dimensional tiling methodology. I/O port locations can be optimized. Versatile support for different layout shapes and port locations makes this system ideal for use in a top-down, fully automatic physical design system. Transistor routing is provided by a novel, recursive version of the A-Star search procedure. This technique reduces the frequency and seriousness of routing blockages by finding near-optimal compromises between new connections and reroutes of previous connections. Routing occurs in two metal layers plus polysilicon and diffusion, and is easily extendable to any number of routing layers. Routing priority can be given to critical nodes. >