Transistor Inverter Research Articles

Sensitivity analysis of an inverted T-shaped vertical tunneling field effect transistor biosensor based on inserted finger type

This paper presents a biosensor based on a finger-inserted inverted T-shaped vertical tunneling field effect transistor (FP-T-TFET). In order to improve the sensitivity and performance of the biosensor, a finger-inserted contact between the source and the channel is used. A comparative analysis between the biosensor based on FP-T-TFET and conventional inverted T-shaped TFET (T-TFET) is simulated for the electrical properties and sensitivity of neutral biomolecules with different dielectric constants and charged biomolecules with different charge densities. The noise analysis of the proposed structure is also performed. Then, the effects of insertion finger distribution, cavity size and filling volume on the performance of FP-T-TFET are investigated. Finally, the structure was subjected to linear analysis, in which the pearson coefficient was 0.92, indicating that the structure has good linear correlation. The results show that the FP-T-TFET biosensor has higher sensitivity in detecting various neutral and charged biomolecules. All device simulations were performed in the TCAD environment with a well-calibrated structure.

РОЗРАХУНОК РЕГУЛЮВАЛЬНИХ ХАРАКТЕРИСТИК РЕЗОНАНСНИХ ПЕРЕТВОРЮВАЧІВ МЕТОДОМ СУПЕРПОЗИЦІЇ

The work presents the calculations of the control characteristics of the full-bridge resonant converter with a series resonant LLC circuit and frequency control by two methods - the first harmonic method and the superposition method. The theoretical results were verified by the analytical-structural modeling method. The power circuit of the resonant converter for the analysis of electromagnetic processes is replaced by a linear T-shaped circuit with two series resonant RLC-circuits and equivalent generators of rectangular voltages, which simulate a transistor inverter and a diode rectifier in the quasi-continuous current mode. Analytical-structural modeling method consists in partly analytical and partly structural ways of building a numerical model of the resonant converter in the form of the simulation model in the MATLAB-Simulink environment. Linear structural links of the model are created on the basis of integral equations of circles. Non-linear links are created based on the non-linear functions and causal relationships. The structural model based on these links takes into account the nonlinearity of the elements of the power circuit of the resonant converter and is based on simpler mathematical expressions compared to the equivalent mathematical model of the resonant converter. The structural model corresponds to the idea of the resonant converter in the form of the resonant circuit with independent equivalent voltage generators and allows to adjust the magnetic coupling coefficient between the transformer windings and simulate processes with arbitrary control functions of equivalent generators. The peculiarity of the use of the superposition method for calculating the static characteristics of the resonant converter is the need to match the voltage phases of the equivalent generators of the equivalent circuit during the changes of the operating frequency or relative load voltage. The dependence of the input voltage of the rectifier, which is simulated by the second equivalent generator, on the processes of the power circuit of the real resonant converter, determines the conditions for matching (adjusting) the phases of the equivalent generators. References 30, figures 5.

Development of method for frequency regulation of output current in high-voltage transformerless resonant chargers of capacitive energy storage devices

The object of research is high-voltage systems of electric discharge installations for various technological purposes. The work reports solving the problem of enabling the rate of charging of a capacitive energy storage, set by the requirements of a certain high-voltage technology. The quantitative characteristics of the deviation of the output current of the resonant inverter from the set stabilized value when changing the switching frequency of inverter switches in the range of output voltage change from 0 to 20 kV were determined. Using the Fourier transform of the rectangular input voltage, the frequency regulation possibility of the output current of the charger for capacitive energy storage devices was analyzed. Estimation dependences of the output current of resonant inverter on the load resistance and frequency deviation from resonant frequency were derived. These dependences could be used to implement frequency control over the switching inverter transistors, with the help of which the given effective value of the output current of the resonant inverter is obtained. A method of frequency regulation of the output current in high-voltage transformerless resonant charging devices of capacitive energy storage devices has been developed. Special feature of this method is that it is based on the frequency dependence of reactive resistances of the inductance and capacitance of the resonant circuit connected in series. Owing to that, it makes it possible to adjust the switching frequency of the inverter’s power switches depending on the relative resistance of the load and the specified growth rate of the capacitive energy storage voltage. The results reported here could be used in the design of benches for testing the electrical strength of high-voltage cables, as well as for the construction of high-voltage transformerless chargers in systems of electric discharge impulse processing of materials

Analysis of high‐frequency electromagnetic ringing phenomenon under GaN‐FET inverter excitation

AbstractIn this study, the ringing phenomenon of gallium nitride‐field effect transistor (GaN‐FET) and silicon‐insulated gate bipolar transistor (Si‐IGBT) inverter excitations in a ring sample was thoroughly measured and analyzed by using a high‐quality oscilloscope with a very high sampling rate of 5 giga‐samples per second (GS/s). Owing to the rapid switching of the GaN‐FET power devices in several nanoseconds and the ringing frequencies in the MHz range, the use of the high sampling rate of 5 GS/s is necessary and useful for accurate measurement. The experimental findings and analysis reveal the following three key points: (i) there are two possible types of high‐frequency resonance phenomena, that is, the first one caused by semiconductor devices and circuits and the other generated by the resonance with loads in use. (ii) The ringing phenomenon because of the resonance under the load is considered to be due to the rising time of pulses that are caused by the rapid switching of the semiconductor devices. (iii) The ability to measure and the two types of ringing phenomena depends on the intensity of the white noise of the measuring instrument

Колебания частоты вращения электрических машин в системах с преобразователями частоты и алгоритмы подавления колебаний

Electromechanical processes in systems with frequency converters and electric machines, which are characterized by fluctuations in machine speeds, currents and voltages, are considered. In drives with rectifiers, capacitor filters, transistor inverters and asynchronous motors in some cases there are fluctuations of filter voltages and motor speeds, leading to emergency shutdown. In systems with thyristor frequency inverters with a DC link and synchronous machines at the start-up of machines in the zones of artificial commutation there are fluctuations of rotation frequencies and currents, which can also lead to emergency shutdown. A control algorithm based on the use of oscillations of constant capacitor voltages in transistor drives or excitation voltages of synchronous machines and the effect of these oscillations on the frequency of inverter control pulses is proposed.

Single PCB sensor-based output current reproduction for three-phase inverter systems

This study proposes a practical output current measurement system in a three-phase inverter with a single printed circuit board (PCB) Rogowski coil sensor inserted in the bus between the DC-link capacitor and the power semiconductor module. This system demonstrates its advantage over conventional output current sensors, such as the Hall effect current sensors, in terms of the size, weight, operation temperature and cost. The system can be applied to 6-in-1 power modules as it does not require sensors in the inverter phase legs.In our previous works, we have developed a method called “envelope tracking”, which is used in this system as well. This method traces the switching current instead of the output current to reproduce the output current signal in real-time. Envelope tracking successfully reproduced the output current waveform for single phase inverters under certain conditions. However, a large error is observed in the three-phase inverter demonstration under a high switching frequency (narrow pulse) or when the switching of different phases overlap each other. These errors must be completely suppressed to implement the system for feedback control in three-phase inverters.In this study, a new analog basis output current waveform reproduction system is introduced to suppress the above mentioned errors. This system is implemented in a three-phase insulated-gate bipolar transistor (IGBT) inverter and successfully reproduces the output current with a single PCB sensor inserted between a 6-in-1 IGBT power module and DC-link capacitor, operating under a switching frequency of 3.5–7.0 kHz and output current of 6 A with DC-link voltage of 150 V.

Charge-plasma-based inverted T-shaped source-metal dual-line tunneling FET with improved performance at 0.5 V operation

In this paper, a charge plasma-based inverted T-shaped source-metal dual line-tunneling field-effect transistor (CP-ITSM-DLTFET) has been proposed to improve the ON current (ION) by increasing the line-tunneling area. In the proposed structure, the charge plasma technique is used to induce the dopants in the source and drain regions. Due to its doping-less structure, the proposed CP-ITSM-DLTFET is immune to random dopant fluctuations and does not require an expensive thermal annealing technique. This makes the proposed device’s fabrication easier and more efficient. The proposed CP-ITSM-DLTFET comprises an inverted T-shaped source metal (sandwiched between the Si-channel) and creates gate-to-source overlap and increases the tunneling area vertically on both sides of the Si-channel. The vertical line-tunneling area in the proposed structure makes the device able to be aggressively scaled compared to conventional TFETs for future technology. The proposed CP-ITSM-DLTFET outperforms almost all pre-existing dopingless TFETs in terms of DC and RF parameters. The switching performance (like high ION = 31.88 uA um−1, steeper AVSS = 23.42 mV dec−1 (over 12-order of drain current), and high ION/IOFF ratio of 1.6 × 1013) and the RF performance (like transconductance (gm) = 0.37 mS, Cut-off frequency (fT) = 90.18 GHz, and Gain Bandwidth product (GBW) = 32.3 GHz) of the proposed CP-ITSM-DLTFET are superior to almost all pre-existing Si, SiGe, and Ge based doping-less TFETs. Moreover, the proposed CP-ITSM-DLTFET-based CMOS inverter has also been comprehensively studied in the paper, showing a good noise margin NMH = 0.198 V (39.8% of VDD) and NML = 0.206 V (41.2% of VDD) with a high voltage gain of 30.25 at VDD = 0.5 V, suggesting great potential for future low power applications.

Application of novel double-layer micro-jet heat sinks for energy-efficient thermal management of motor inverters in electric vehicles

The relentless advancement in electronics miniaturization and performance has birthed a tremendous amount of heat flux, demanding effective dissipation techniques. Thermal effects pose a significant hurdle in the thermal management of electric vehicles (EVs) and having advanced cooling techniques in place is vital. To tackle this, the present study numerically evaluates the cooling attributes of two novel double-layer micro-jet heat sinks (DLMJHSs) to address the thermal management of insulated-gate bipolar transistors (IGBTs) in the motor inverters of EVs. The numerical analyses are carried out for Reynolds numbers ranging from 5000 to 25,000, IGBT heat fluxes of 100, 200, and 300 W/cm2, and different configurations of DLMJHSs. The potential of using nanofluids is assessed by employing Al2O3–water nanofluid with different volume fractions of 0.8% and 1.7%. The finite volume technique is implemented to solve the equations and the turbulence closure is modeled using the k-ԑ model. Results show that HS #2 provides a 10.2% higher convective heat transfer coefficient leading to a 7.44 ℃ lower baseplate temperature than HS #1. Besides, HS #2 prevents the occurrence of high-temperature spots owing to a more uniform temperature distribution in comparison with HS #1. HS #2 demonstrates the most uniform temperature distribution, with a Coefficient of Variation of only 0.00993 and a maximum heat transfer coefficient of 80.5 kW/m2 ℃. The heat sink’s baseplate temperature drops by increasing either the Reynolds number or the volume fraction. The baseplate temperature declines by up to 6.94 ℃ using a nanofluid volume fraction of 1.7% compared with only the base fluid. A minimum Reynolds number of 15,700 is required to prevent overheating at the peak heat flux. The performance evaluation criterion (PEC) is higher than 1 for Re ≤ 15,000.

Simple Enhancement of Series–Series-Compensated Inductive Wireless Power Transfer Links Operating With Load-Independent Voltage Output at Fixed Frequency to Attain Zero Inverter Phase Angle

It is well-known that series-series compensated resonant inductive wireless power transfer links (SS-IWPTL) may be designed to attain load independent voltage output (LIVO) for given operating frequency and coupling coefficient. Unfortunately, corresponding inverter output impedance is either highly-inductive or highly-capacitive (inductive region is typically preferred due to natural zero-voltage switching (ZVS) of inverter transistors), significantly increasing inverter volt-ampere (VA) rating. The letter demonstrates that designing the SS-IWPTL for operation in the capacitive region and then adding a shunt inductor across AC-side terminals of either inverter or rectifier while allows attaining inverter zero phase angle (ZPA) thus minimizing its VA rating.

Структурное моделирование существующих и усовершенствованных алгоритмов управления тиристорных переключающих устройств агрегатов бесперебойного питания собственных нужд атомных станций

The article analyzes the operation of thyristor automatic switching devices for uninterruptible power supply units of nuclear power plants. They are part of the emergency power supply system for auxiliary electrical equipment with a rated voltage of 0.4 kV. In such a reliable power supply system for especially responsible consumers, alternative networks and backup sources are necessarily used. Typically, groups of consumers for auxiliary needs of nuclear power plants are powered from the inverter network, so that in the event of a shutdown of the backup bypass network, these loads continue to be powered by the uninterruptible power supply unit. It incorporates a charger – a controlled rectifier, a battery pack and a transistor inverter. The transition from one network to another in any direction must be “shockless” in order to avoid the operation of the protections of uninterruptible power units and other electrical protections of the reliable power supply system. If there are failures in the algorithms or their irrational organization, the processes of transition between networks may be accompanied by a violation of uninterrupted power supply or phase-to-phase short circuits. A structural simulation model has been created in the MatLab computer mathematics system for testing transition algorithms for various phase shifts of networks and transition directions. The algorithm of transition between networks for uninterruptible power units of one of the manufacturing companies that supplied equipment to nuclear power plants was analyzed. A safer optimal algorithm for controlling network switching with phase-by-phase control of the current drop in the disconnected network is proposed. The proposals are supported by the results of computer simulations.

Track and hunt metaheuristic based deep neural network based fault diagnosis model for the voltage source inverter under varying load conditions

Induction motors act as the pillars for industries and are preferable in various applications due to the characteristics of stability and sturdiness. The stability level should be efficiently maintained in order to monitor and analyze the faults that occur in three-phase Voltage Source Inverter. In this research, fault prediction occurs in the inverter under various load conditions is performed using the proposed track and hunt meta-heuristic-based deep neural network. The open circuit fault is generated in the three-phase voltage source inverter transistor under varying load conditions and is determined using the proposed track and hunt optimization. The proposed track and hunt meta-heuristic is developed by hybridizing the characteristics of hunting and tracking. After the data acquisition, the features are extracted from the collected faulty data in the form of three-phase current, voltage, torque, and speed. The Deep Neural Network classifier is trained using the obtained features and the faulty switches are identified through the average value of the three-phase current. The three-phase induction motor is connected as a load for the voltage source inverter with reference to the frequency variation. The prediction performance of track and hunt- deep learning classifier reveals that the percentage improvement of 10–15% is acquired for the developed method.

A 1T2M memristor-based logic circuit and its applications

A 1T2M logic gate design inspired by MRL logic is presented in this paper and a variety of applications based on 1T2M units are promoted. The innovation of this topic is to use the non-volatile nature of memristors with the advantage of small area and volume to constitute a NOT logic with storage function for bridging the gap of memristor-based circuits in the design of NOT gates with the MRL structure instead of transistors in conventional inverters. 1T2M is used in the improved XOR/XNOR logic, and on this basis the combinational logic circuit is designed so as to adapt to more digital circuit, in which the consumption is reduced by the high proportion of memristor in circuit. The implementations of the 1T2M structure demonstrates that 1T2M cell makes an excellent contribution to reducing circuit area and consumption through multiple comparisons. Thus the way is paved for simulating the logic function of dendrites and implementing artificial neural networks at large scale.

Design and Functional Test of Transistor Inverter Based on Polyvinyl Alcohol and Graphene Oxide Electrolyte

Eco‐friendly “green” electronics are attracting increasing interest in recent years. For example, neural prostheses, nerve implants, drug delivery devices, and diagnostic electronics, as well as some green materials (paper, silk, and polysaccharides) with bioabsorbable and biocompatible transistors, load inverters, and other devices. Here, biodegradable polyvinyl alcohol (PVA)/graphene oxide (GO) electric double‐layer (EDL) transistors are prepared on glass substrates. PVA film treated with GO solution is used as a gate dielectric. Oxide EDL transistors show good performance. A resistive load inverter is also constructed, which shows full swing characteristics and high voltage gain at low operating voltage. The waveform conversion is realized, including the conversion from sine wave to rectangular wave, and the conversion from noise signal to two‐bit output. In addition, PVA/GO transistors can be easily dissolved in water. The proposed PVA/GO oxide transistors may have potential applications in “green” portable devices.

Effect of temperature on heavy ion-induced single event transient on 16-nm FinFET inverter chains

The variations of single event transient (SET) pulse width of high-LET heavy ion irradiation in 16-nm-thick bulk silicon fin field-effect transistor (FinFET) inverter chains with different driven strengths are measured at different temperatures. Three-dimensional (3D) technology computer-aided design simulations are carried out to study the SET pulse width and saturation current varying with temperature. Experimental and simulation results indicate that the increase in temperature will enhance the parasitic bipolar effect of bulk FinFET technology, resulting in the increase of SET pulse width. On the other hand, the increase of inverter driven strength will change the layout topology, which has a complex influence on the SET temperature effects of FinFET inverter chains. The experimental and simulation results show that the device with the strongest driven strength has the least dependence on temperature.

Design and investigation of stability‐ and power‐improved 11T SRAM cell for low‐power devices

AbstractThe modern system‐on‐chips require stable and low‐power SRAM cells due to technology scaling and limited sources of energy. Therefore, a stability‐ and power‐improved 11T SRAM cell is proposed in this study. The proposed cell core is composed of a strong cross‐coupled structure of a conventional inverter with a N‐type stacked transistor and a Schmitt‐trigger (ST) with a double channel‐length pull‐up network. This coupled with a separate read path enhances the read static noise margin (RSNM). Moreover, a feedback‐cutting N‐type transistor is placed inside the cell core to improve the write static noise margin (WSNM)/write margin (WM). Though the presence of stacked transistors in access paths increases read delay (TRA)/write delay (TWA), it reduces leakage. This metric further minimizes with the aid of a stacked structure of latch core and double channel‐length of pull‐up transistor in the ST inverter. The moderate read/write frequency and single‐ended structure of the suggested cell result in low dynamic power. Simulated results by using 16‐nm CMOS at VDD = 0.7 V show that the proposed cell has the second‐best RSNM/WSNM, which is 4.65/1.44 times higher than that of the fully differential 8T (FD8T) cell, as the basic cell. Moreover, it reduces leakage power by at least 2.01 times and consumes moderate read/write power, nearly 1.44/1.81 times lower than that of FD8T cell, at the cost of 1.61 times area overhead. The proposed cell can eliminate read/write‐half‐select‐disturbance issues to support bit‐interleaving architecture to increase soft error immunity.

Performance Enhancement of ICN-Based Single-Stage AC–DC Converters Using Reconfigurable Inverters

This article presents a reconfigurable inverter design for the recently proposed impedance control network (ICN) based single-stage ac–dc converters, targeting improvement in their efficiency and power density. This reconfigurable-inverter design effectively compresses the range of input voltages to the ICN converter by operating its two inverters in parallel at low line and in a stacked fashion at high line input. In addition to retaining the wide range zero voltage switching and near zero current switching operation characteristic of the ICN converter, the proposed reconfigurable inverter design benefits all the converter's transistors and magnetic components as it simultaneously reduces the peak voltage stress on its inverter transistors, rms currents through its rectifier transistors, the resonant inductance requirement, and the step-down burden on its transformer, thus improving the overall performance. A novel active voltage balancing scheme for the stacked mode of operation of the two inverters is also proposed. An enhanced version of this active voltage balancing strategy is also discussed, which ensures soft-switching of the inverter transistors by deliberately introducing slight inverter voltage imbalances of appropriate magnitude. A universal-input (90–265 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> ), 20-V output, 330-W, 300-kHz reconfigurable-inverter-based ICN ac–dc converter prototype is built and tested. This prototype achieves a power density of 44.5 W/in <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> , and peak efficiencies of 94% at low line (120 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> ) and 93.8% at high line (230 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> ). Compared to the basic ICN converter prototype, this prototype achieves 17% higher power density and has 23% and 9% less loss at low and high line input, respectively.

Characterization of charge sharing induced by high LET heavy ions using inverter chains in a commercial bulk FinFET process

The inverter is one of the most important cell types in any standard cell library at each technology node, and it is also very important for single-event research. The distributions and cross-sections of single-event transients (SETs) and single-event multiple transients (SEMTs) were characterized using 14/16 nm bulk fin field-effect transistor (FinFET) inverters under heavy ion radiation. An inverter with double driving strength (INVX2) was used as an instantiate object to observe the SET and SEMT response. 181Ta with energies of 1891 GeV and 2000.5 MeV were used respectively in the experiments, of which the linear energy transfer (LET) values were 87.4 MeV cm2 mg−1 and 75.4 MeV cm2 mg−1. The test results indicated that: (a) the mean pulse widths of the SET and SEMT were less than 100 ps, and decreased with LET decreasing; (b) there was charge sharing between abutted INVX2 inverters placed horizontally, and the generation probability of SEMT induced by charge sharing was less than 1% even if the LET of heavy ion reached 87.4 MeV cm2 mg−1. The results were beneficial for a better understanding of SET and SEMT tolerance for inverters in FinFET technology.

A Reliable Low Standby Power 10T SRAM Cell With Expanded Static Noise Margins

This paper explores a low standby power 10T (LP10T) SRAM cell with high read stability and write-ability (RSNM/WSNM/WM). The proposed LP10T SRAM cell uses a strong cross-coupled structure consisting standard inverter with a stacked transistor and Schmitt-trigger inverter with a double-length pull-up transistor. This along with the read path separated from true internal storage nodes eliminates the read-disturbance. Furthermore, it performs its write operation in pseudo differential form through write bitline and control signal with a write-assist technique. To estimate the proposed LP10T SRAM cell’s performance, it is compared with some state-of-the-art SRAM cells using HSPICE in 16-nm CMOS predictive technology model at 0.7 V supply voltage under harsh manufacturing process, voltage, and temperature variations. The proposed SRAM cell offers 4.65X/1.57X/1.46X improvement in RSNM/WSNM/WM and 4.40X/1.69X narrower spread in RSNM/WM compared to the conventional 6T SRAM cell. Furthermore, it shows 1.26X/1.08X/1.01X higher RSNM/WSNM/WM and 1.71X/1.25X tighter/wider spread in RSNM/WM compared to the best studied SRAM cells. The proposed SRAM cell indicates 74.48%/1.41% higher/lower read/write delay compared to the 6T SRAM cell. Moreover, it exhibits the third-(second-) best read (write) dynamic power, consuming 29.69% (26.87%) lower than the 6T SRAM cell. The leakage power is minimized by the proposed design, which is 37.35% and 12.08% lower than that of the 6T and best studied cells, respectively. Nonetheless, the proposed LP10T SRAM cell occupies 1.313X higher area compared to the 6T SRAM cell.

СИСТЕМА ЦИФРОВОГО ФАЗОВОГО АВТОМАТИЧНОГО ПІДСТРОЮВАННЯ ЧАСТОТИ РЕЗОНАНСНОГО ІНВЕРТОРА НАПРУГИ

The digital phase-locked loop (PLL) system for the resonant voltage inverter with pulse density modulation of induction heating installations is developed. The proposed system for frequency determination uses the feedback signal on the collector-emitter (drain-source) voltage of the inverter transistors and on the output current of the inverter, and stores this frequency on the interval of zero output voltage. A study of the PLL system in different operating modes when changing the load parameters is presented. References 8, figures 6, table 1.

Influence of the Placement Accuracy of the Brushless DC Motor Hall Sensor on Inverter Transistor Losses

Low-power BLDC motors are often and willingly used in many drive devices due to their functional advantages. They are also used in advanced positioning systems, where their good dynamic performance parameters are used. The control systems use shaft position sensors mounted on motors, the structure of which is based on magnetic elements and Hall sensors. The aim of this article was to investigate the influence of the BLDC motor quality on the correct operation of the control semiconductor system. The article presents the effect of BLDC motor shaft observation system’s inaccuracies on the friction and current amplitudes of individual inverter keys. Waveforms of the controller phase currents are considered and recorded on a test bench that allows precise sensor position changes. In addition, the effect of sensor misalignment on power losses in individual inverter transistors is investigated. The article shows a significant influence of the motor shaft observation system’s assembly accuracy on the current amplitudes of individual driver transistors and their power losses, which makes it necessary to consider these parameters when constructing power electronic systems.