Transistor Differential Pair Research Articles

Analog neuromorphic circuit for spontaneous Ca2+ oscillations

This study proposes an innovative analog neuromorphic circuit design to mimic spontaneous Ca2+ oscillations observed in astrocytes. Unlike traditional models, this approach does not rely on synaptic stimulation, suggesting that astrocytes may play a key role in generating neuronal activity. The circuit is built using transistor differential pairs to approximate the nonlinear sigmoidal biological functions, and its performance is validated through simulation and compared against mathematical models using phase diagram analysis. Results indicate a good fit between the circuit and the mathematical model. Finally, the circuit’s ability to simulate the release of glutamate and ATP through spontaneous oscillations is demonstrated.

Toward Realization of 2.4 GHz Balunless Narrowband Receiver Front-End for Short Range Wireless Applications.

The demand for radio frequency (RF) transceivers operating at 2.4 GHz band has attracted considerable research interest due to the advancement in short range wireless technologies. The performance of RF transceivers depends heavily on the transmitter and receiver front-ends. The receiver front-end is comprised of a low-noise amplifier (LNA) and a downconversion mixer. There are very few designs that focus on connecting the single-ended output LNA to a double-balanced mixer without the use of on-chip transformer, also known as a balun. The objective of designing such a receiver front-end is to achieve high integration and low power consumption. To meet these requirements, we present the design of fully-integrated 2.4 GHz receiver front-end, consisting of a narrow-band LNA and a double balanced mixer without using a balun. Here, the single-ended RF output signal of the LNA is translated into differential signal using an NMOS-PMOS (n-channel metal-oxide-semiconductor, p-channel metal-oxide-semiconductor) transistor differential pair instead of the conventional NMOS-NMOS transistor configuration, for the RF amplification stage of the double-balanced mixer. The proposed receiver circuit fabricated using TSMC 0.18 µm CMOS technology operates at 2.4 GHz and produces an output signal at 300 MHz. The fabricated receiver achieves a gain of 16.3 dB and consumes only 6.74 mW operating at 1.5 V, while utilizing 2.08 mm2 of chip area. Measurement results demonstrate the effectiveness and suitability of the proposed receiver for short-range wireless applications, such as in wireless sensor network (WSN).

낮은 DNL 특성을 가진 8b 2단 Folding A/D 변환기

In this research, a 8-bit CMOS 2 stage folding A/D converter is designed, For low power consumption and small chip size, the A/D converter is designed by using folding and interpolation circuit. Folding circuit is composed of the transistor differential pairs which are connected in parallel. It reduces the number of comparator drastically. The analog block composed of folding block, current interpolation circuit, and three stage current comparator is designed with differential-mode for high speed operation. The simulation in a CMOS process. shows DNL and SNDR of 0.5LSB and 47 dB at 250 MHz/s sampling frequency.

A pseudologarithmic rectifier using unbalanced bias MFMOS differential pairs

A pseudologarithmic rectifier using multi-input floating-gate MOS (MFMOS) transistors is presented in this paper. The rectifiers consist of unbalanced bias matched MFMOS transistor differential pairs. The transfer characteristics of each subrectifier are determined by an appropriate choice of transistor aspect ratio and capacitive input coupling ratio such that in the summation of the output currents from each rectifier stage, the overall transfer characteristics closely approximates that of a true logarithmic behavior. It is operable at low supply voltage (/spl plusmn/0.9 V) and has low temperature dependence. Measured dynamic range of 27 dB and 16.5 dB, with a corresponding logarithmic error of /spl plusmn/0.7 dB and /spl plusmn/0.35 dB, has been obtained for three-stage and two-stage pseudologarithmic rectifiers, respectively, at room temperature. The measured logarithmic error for the three-stage pseudologarithmic rectifier at 125/spl deg/C is /spl plusmn/1.05 dB which is an increase of /spl plusmn/0.35 dB over a 100/spl deg/C range.

Highly-linear transconductor cell realised by double MOS transistor differential pairs

A novel scheme for tunable transconductance cells with high linearity is described. The proposed configuration is realised by double MOS transistor differential pairs with two independent linear outputs, which can be employed separately as well as in a parallel or cross-coupled connection. A trans-conductance amplifier is shown as an application example. Computer simulation is used to verify the concept.

Fully differential operational amplifiers using CMOS compatible ateral bipolar transistors with improved common-mode regulation

A new bias circuit for a CMOS compatible lateral bipolar transistor differential pair is presented. The circuit compensates for all process and bias dependent variations of the lateral collector current to emitter current ratio α. Experimental results show that its application to a fully differential amplifier improves the precision of the common-mode output voltage regulation by at least an order of magnitude.

A sinusoidal RC-oscillator with amplitude control by current splitting

Abstract The paper describes a method of amplitude control in a sinusoidal RC-oscillator. The oscillator includes an amplifier of current with differential output and the amplitude control is achieved by insertion of a current splitter in the positive feedback path. The current splitter is realized as a bipolar transistor differential pair with control of emitter tail current splitting from an amplitude detector. The approach is suitable for design of RC-oscillators operating with a low voltage power supply (an example of the oscillator for a 3 V power supply is given).

Differential amplifiers that reject common-mode currents

The transistor differential pair is analyzed and it is shown that the common mode rejection ratio (CMRR) is limited both in magnitude and bandwidth by device parameters. The performance is not significantly improved by series common-mode feedback. It is shown that amplifiers with shunt common-mode feedback reject common-mode input currents and that their common-mode rejection ratio can be made independent of device parameters. Applications of such amplifiers include differential operational amplifiers, rejection of large common-mode voltages, and transducer amplifiers. Basic circuitry is described and the performance of a practical circuit is given.

Sinusoidal burst generator for auditory evoked response research.

A simple stimulator has been devised in which sinusoidal signals in the audio range are linearly modulated to generate tone bursts of controlled duration and shape for auditory research. The stimulator comprises a transistor differential pair modulator whose differential collector voltage is the product of the voltage applied at a base (sine wave input) and the emitter current (varied by the modulating waveform). A trapezoidal generator is provided for the modulating waveform. The output is greater than 60 dB above noise and switching transients and the ON-OFF ratio is greater than 60 dB up to 50 kHz. The frequency response is flat to 50 kHz, and there is no appreciable distortion. The trapezoidal generator has equal rise and fall times which are independent of the flat-top duration.