Transimpedance Amplifier Stage Research Articles

First test results of the trans-impedance amplifier stage of the ultra-fast HPSoC ASIC

We present the first results from the HPSoC ASIC designed for readout of Ultra-fast Silicon Detectors. The 4-channel ASIC manufactured in 65 nm CMOS by TSMC has been optimized for 50 μm thick AC-LGAD. The evaluation of the analog front end with β-particles impinging on 3 × 3 AC-LGAD arrays (500 μm pitch, 200 × 200 μm2 metal) confirms a fast output rise time of 600 ps and good timing performance with a jitter of 45 ps. Further calibration experiments and TCT laser studies indicate some gain limitations that are being investigated and are driving the design of the second-generation pre-amplification stages to reach a jitter of 15 ps.

Design Considerations of Reconfigurable CMOS Mixers for Multi-Standard Communication Receiver Systems

This paper has been carried out the study of reconfigurable wide-band mixers that can do the frequency conversion and gain variation standards with low noise and high linearity used in multi-mode and multi-standard receivers. Over the last few years reconfigurability has become very popular in adopting technology to meet the wideband wireless communication specifications that is compatible with multi-standards like GPS (1.57 GHz), WLAN (2.4 GHz - 5.9 GHz), Bluetooth (2.402 – 2.483 GHz) and ZigBee (0.784 - 0.915 GHz) in low power consumption environment. The reconfigurability can be achieved between low and high band modes through power switching in RF frequency mixers. It can be achieved by flipping the input RF signal between gate and source terminal of input transistor and altering the trans-impedance stage output. With the concept of reconfigurable transistor pair with open and short circuit stubs, one can not only find the configurable gain with center frequencies 7.355, 8.65, 11.35 and 12.65 GHz but also with high power efficiency. Tow Thomas Bi-Quad Topology other than the traditional current commuting technique for the second order trans-impedance amplifier stage, works as a current mode filter over a tunable bandwidth. The active Gilbert mixers are used widely in most of communication system, due to its significance gain, perfect isolation, and linearity in response.

Design Considerations of Reconfigurable CMOS Mixers for Multi-Standard Communication Receiver Systems

This paper has been carried out the study of reconfigurable wide-band mixers that can do the frequency conversion and gain variation standards with low noise and high linearity used in multi-mode and multi-standard receivers. Over the last few years reconfigurability has become very popular in adopting technology to meet the wideband wireless communication specifications that is compatible with multi-standards like GPS (1.57 GHz), WLAN (2.4 GHz - 5.9 GHz), Bluetooth (2.402 – 2.483 GHz) and ZigBee (0.784 - 0.915 GHz) in low power consumption environment. The reconfigurability can be achieved between low and high band modes through power switching in RF frequency mixers. It can be achieved by flipping the input RF signal between gate and source terminal of input transistor and altering the trans-impedance stage output. With the concept of reconfigurable transistor pair with open and short circuit stubs, one can not only find the configurable gain with center frequencies 7.355, 8.65, 11.35 and 12.65 GHz but also with high power efficiency. Tow Thomas Bi-Quad Topology other than the traditional current commuting technique for the second order trans-impedance amplifier stage, works as a current mode filter over a tunable bandwidth. The active Gilbert mixers are used widely in most of communication system, due to its significance gain, perfect isolation, and linearity in response.

A Study on Transimpedance Amplifier in 0. 35 µm CMOS Technology

This paper presents a design of the transimpedance amplifier using 0.35µm CMOS technology. In the proposed transimpedance amplifier, feedback resistor RF of conventional transimpedance amplifier has been replaced by NMOS transistor as an active feedback resistor. This circuit operates at 3.3V power supply voltage and for a photocurrent of 0.5µA.The proposed transimpedance amplifier having low noise, high gain and large dynamic range. The simulated results of transimpedance gain in single stage and three stage transimpedance amplifiers is 4.43 MΩ and 4.39 MΩ at gate voltage of 0.4V. Power dissipation of single stage and three stage transimpedance amplifier is 602.04 µW and 1.781mW at gate voltage of 2.0V.

A Passive Mixer for a Wideband TV Tuner

This brief presents the design of a direct conversion mixer for a wideband television tuner operating at 48-860 MHz. The mixer consists of a transconductance stage, a passive current switching stage, and a transimpedance amplifier stage. In the switching stage, by adopting an opposite phase auxiliary switching quad configured in parallel with the main switching quad, the unwanted harmonics at the output of the switching stage are suppressed, thereby preventing mixer linearity degradation at low input frequencies. The proposed mixer is implemented in a 0.13-μm CMOS technology, and measurements show more than a 19.5-dB voltage gain, 12-dB noise figure, and 8-dBm IIP3 over the entire operating band of 48-860 MHz while dissipating 4.5 mA from a 1.2-V supply.

A CMOS imaging diversity receiver for gigabit free-space optical MIMO

A 7-channel imaging diversity receiver based on current-summing is implemented in a 180 nm CMOS technology for broadband free-space optical (FSO) multi-input/multi-output (MIMO) communication. Each channel employs a low input-impedance current mirror (CM) as the input stage, which allows the implementation of direct current-summing for equal-gain combining (EGC). The summed current signal drives a second stage transimpedance amplifier (TIA) to generate the output voltage. Electrical characterization was performed using a photodiode emulation circuit and chip-on-board FR-4 assembly, demonstrating a total transimpedance gain of 62 dB?, ?3 dB bandwidth of 1.2 GHz, and eye diagrams up to 2 Gb/s for 0.25 pF photodiode capacitance. The theoretical sensitivity of the imaging receiver is ?16.8 dBm for a bit error rate (BER) of 10?9 at a photodetector responsivity of 0.4 A/W. The simulated power consumption for a single front-end amplifier circuit is 4.2 mW, and for the second stage TIA is 10.3 mW from a single 1.8 V supply. The diversity receiver is flip-chip compatible to enable hybrid integration to a custom InGaAs photodetector array.

Analysis of free-space optical interconnects for the three-dimensional optoelectronic stacked processor

Performance of free-space optical interconnect for the three-dimensional optoelectronic stacked processor (3DOESP) has been analyzed. The wave propagation in the optical interconnection system has been investigated by utilizing rigorous scalar diffraction theory. The effects of ghost talk caused by the superposition of the delayed reflections of the original signal due to the multiple propagation of the wave between the vertical-cavity surface-emitting laser (VCSEL) and metal-semiconductor-metal (MSM) detector have been analyzed. The conducted study indicates that even in the presence of significant amount of ghost talk a high performance free-space optical interconnect can be realized in this system by employing a receiver architecture that allows for DC level adjustment of the signal at the input of the transimpedance amplifier stage.

A transimpedance amplifier using a novel current mode feedback loop

We present a transimpedance amplifier stage based on a novel current mode feedback topology. This circuit employs exclusively NMOS and PMOS transistors and requires no capacitor to stabilize the transimpedance loop and no resistor for the transresistance feedback and transistor loading. This amplifier circuit is fully compatible with submicron digital CMOS processes. The active feedback network consists of two grounded gate MOS devices which split the output current in the feedback branch and the output branch. The transresistance and the phase margin are adjustable via external DC signals. The measured rise time of the impulse response of the amplifier implemented in an industrial 0.7 μm CMOS process is 18 ns for a transresistance of 180 kΩ and 30 ns for a transresistance of 560 kΩ. The measured Equivalent Noise Charge (ENC) is 800 rms e for an input capacitance of 20 pF with the transresistance adjusted to 560 kΩ.