Transient Fault Tolerance Research Articles

A simulation methodology for verification of transient fault tolerance of ASICs designed for high-energy physics experiments

Transient fault tolerance verification is a crucial step in the design of radiation-tolerant ASICs for high-energy physics experiments. In this paper, we discuss a methodical approach toward the verification of transient fault tolerance of ASICs using industry-standard methodologies and tools. The framework for fault verification includes tools for fault enumeration, fault injection, and running fault campaigns. The framework supports fault verification at various levels of design abstraction from high-level register-transfer model to gate-level netlist. The methodology and framework described in this paper were successfully used to identify SEE vulnerabilities in various ASICs designed at CERN.

Nonlinear robust fault-tolerant control for turbofan engines with actuator faults

This paper investigates nonlinear robust fault-tolerant control for turbofan engines with actuator faults. The nonlinear robust fault-tolerant control method is proposed in this paper, which can guarantee the fault tolerance and robustness of turbofan engines when faults and disturbances occur. The design method is implemented in three steps: Firstly, the dynamic effects caused by actuator faults on turbofan engines are analyzed and then the multivariable polynomial state-space model of turbofan engines with actuator faults is proposed. Secondly, appropriate design parameters are chosen according to fault information. Thirdly, the nonlinear robust fault-tolerant control law for turbofan engines with actuator faults is designed by solving an optimization problem. In addition, stability and [Formula: see text] gain-like for turbofan engines with bounded disturbances and actuator faults are guaranteed by the proposed nonlinear robust fault-tolerant control method. The distinctive characteristic of the paper is that the nonlinear robust fault-tolerant control method for turbofan engines against actuator faults is proposed which can relax the accuracy requirements of the fault diagnosis subsystem and improve the fault-tolerant performance of the closed-loop control system. Simulations show that the nonlinear robust fault-tolerant control method has better control performances including transient responses, disturbance rejection, and fault tolerance for the turbofan engine with actuator faults.

Lifetime-aware real-time task scheduling on fault-tolerant mixed-criticality embedded systems

Abstract In recent years, the design of mixed-criticality embedded systems suffering from transient faults has attracted much attention. From the perspective of system users, it is desirable to optimize system lifetime while meeting all design constraints. Existing task scheduling algorithms cannot be utilized to maximize the lifetime of mixed-criticality embedded systems since they do not take into account the impact of providing transient fault tolerance on system lifetime. This paper investigates the problem of prolonging the lifetime of mixed-criticality embedded systems on a uniprocessor equipped with dynamic voltage and frequency scaling (DVFS) technique. The transient faults and thermal cycling incurred permanent faults are simultaneously considered in the system lifetime optimization under the constraints of safety requirements and schedule timeliness. A mixed-integer linear programming (MILP) formulation is first presented to deal with the task scheduling problem. Since the MILP method is a time-consuming solution for large-scale systems, a cross-entropy method based heuristic is then proposed to achieve a better tradeoff between the system lifetime achieved by the derived task schedule and the runtime consumed to generate the task schedule. Experiments based on synthetic and real-world benchmarks are conducted, and simulation results demonstrate that the proposed heuristic improves system lifetime by up to 32.73% with acceptable runtime as compared to benchmarking methods.

Enhancing transient fault tolerance in embedded systems through an OS task level redundancy approach

In numerous safety critical applications, the use of high-reliability or radiation-tolerant equipment may not be a viable option due to the presence of several constraints (such as cost) and the need to utilize Commercial off-the Shelf (COTS) equipment. However, such equipment may not meet reliability requirements, and therefore certain appropriate measures need to be taken to enhance their reliability. In this paper, a fully software-based method is presented to increase the reliability of COTS equipment against transient faults. The reliability of COTS is increased by utilizing a task-level redundancy in operating system. The proposed method is evaluated using a software fault injection method and a full system prototype. The experimental results show that the proposed method increases the fault coverage up to 99.34%. Moreover, the proposed method can be used in embedded systems without any hardware, software, or information redundancy.

Low cost fault tolerance against kc-cycle and km-unit transient for loop based control data flow graphs during physically aware high level synthesis

Recent literatures have proved that current technologies pose grave reliability concern for digital devices due to possibility of multiple (km)-unit transient fault (MTF) and multi (kc)-cycle transient fault (MCT) emanating from particle strike with moderate linear energy transfer (LET). This has arisen due to massive scaling in device dimensions and surge in device frequency happening so far. In the literature solutions for fault tolerant design, that can address MTF and MCT simultaneously during high level synthesis (HLS) for both loop based and non-loop based applications, does not exist. This paper presents the following novel contributions: (a) novel fault tolerant HLS methodology for simultaneously providing multi-cycle (control step) and multi-unit transient fault tolerance for loop based control data flow graphs (b) novel HLS methodology for low cost design solution through exploration of fault tolerant hardware configuration and loop unrolling factor. Results of the proposed approach on standard benchmarks yielded fault tolerant solutions with significantly reduced design cost (average~27%) and power consumption (average~61%) when compared to a recent similar approach.

Global Optimization of Fixed-Priority Real-Time Systems by RTOS-Aware Control-Flow Analysis

Cyber--physical systems typically target a dedicated purpose; their embedded real-time control system, such as an automotive control unit, is designed with a well-defined set of functionalities. On the software side, this results in a large amount of implicit and explicit static knowledge about the system and its behavior already at compile time. Compilers have become increasingly better at extracting and exploiting such static knowledge. For instance, many optimizations have been lifted up to the interprocedural or even to the whole-program level. However, whole-program optimizations generally stop at the application--kernel boundary: control-flow transitions between different threads are not yet analyzed. In this article, we cross the application--kernel boundary by combining the semantics of a real-time operating system (RTOS) with deterministic fixed-priority scheduling (e.g., OSEK/AUTOSAR, ARINC 653, μITRON, POSIX.4) and the explicit application knowledge to enable system-wide, flow-sensitive compiler optimizations. We present two methods to extract a cross-kernel, control-flow--graph that provides a global view on all possible execution paths of a real-time system. Having this knowledge at hand, we tailor the operating system kernel more closely to the particular application scenario. For the example of a real-world safety-critical control system, we present three possible use cases. (1) Runtime optimizations, by means of specialized system calls for each call site, allow one speed up the kernel execution path by 28% in our benchmark scenario. Furthermore, we target transient hardware fault tolerance with two automated software-based countermeasures: (2) generation of OS state assertions on the expected system behavior, and (3) a system-wide dominator-region based control-flow error detection, both of which leverage significant robustness improvements.

Design and Analysis of Transient Fault Tolerance in SRAM with different NT Techniques

In digital domain applications one of the main important analyses is to check the system performance even if the fault is occurred. This paper describes the fault tolerance technique based on the software approach for SRAM memory unit present in the multi core system using Processor Level Redundancy (PLR). The PLR proceeds with software-centric approach, soft fault tolerance which ensuring a correct software execution. In this approach we applied here only for SRAM available in the processor. This scheme is used at user space level which does not necessitate changes to the original application. In this approach is used to detect the soft errors presented in the memory unit and it will recover from the fault without stop the process of the memory unit. To design the SRAM here we use the different nT technique. The main goal of this approach is which implements fault error detection and fault recovery mechanism to check the performance of the memory unit. This paper presents software based nT for SRAM design and analysis transient fault tolerance using Process Level Redundancy (PLR) is lower when comparable to existed.

Software Implemented Transient Fault Detection

This paper aims to describe how to detect errors in microprocessors (MPs) by checking the processor status word (PSW). Electrical transients often corrupt the bit-patterns in various processor registers. This paper describes a software fix (SF) for the detection of operational faults in a MP or in a micro-controller system through detection of bit errors in PSW. A MP or a micro-controller-based application system can be made a robust one with this proposed SF through establishing a fail-stop kind of transient fault tolerance at a very low cost. The proposed approach is intended to detect MPs’ bit errors during the run-rime of a MP system. The proposed SFs aim to supplement the intrinsic error detection mechanism of a MP. Here, it is not intended to correct bit errors; rather, it is intended to detect bit errors in MP.

Approaches for Transient Fault Tolerance in Multiprocessor - A State of Art

Objectives: This aim of this paper is to analyse different approaches for transient fault tolerance like PBS, RM-FT, FSP, BCE and MWFD. Methods: Transient faults are emerging as a critical issue in the reliability of real time systems. Besides multiprocessors being an apparent part of various booming technologies now-a-days, it becomes evident to make these systems susceptible, reliable and consistent to transient faults. Thus, to address the increasing susceptibility of multiprocessors systems to transient faults, different approaches are analysed to counter transient faults. Findings: To identify the optimal method for various constraints like slack time, reduction in time space and reconfiguration etc. Applications: This comparative analysis will help for us to identify the optimal approaches for tolerating the transient fault in critical real time systems.

Cross-Kernel Control-Flow--Graph Analysis for Event-Driven Real-Time Systems

Embedded real-time control systems generally have a dedicated purpose and fixed set of functionalities. This manifests in a large amount of implicit and explicit static knowledge, available already at compile time. Modern compilers can extract and exploit this information to perform extensive whole-program analyses and interprocedural optimizations. However, these analyses typically end at the application--kernel boundary, thus control-flow transitions between different threads are not covered, yet. This restriction stems from the pessimistic assumption of a probabilistic scheduling policy of the underlying operating system, impeding detailed predictions of the overall system behavior. Real-time operating systems, however, do provide deterministic and exactly specified scheduling decisions, as embedded control systems rely on a timely and precise behavior. In this paper, we present an approach that incorporates the RTOS semantics into the control-flow analysis, to cross the application--kernel boundary. By combining operating system semantics, the static system configuration and the application logic, we determine a cross-kernel control-flow--graph, that provides a global view on all possible execution paths of a real-time system. Having this knowledge at hand, enables us to tailor the operating system kernel more closely to the particular application scenario. On the example of a real-world safety-critical control system, we present two possible use cases: Run-time optimizations, by means of specialized system calls for each call site, allow to speed up the kernel execution path by 33 percent in our benchmark scenario. An automated generation of OS state assertions on the expected system behavior, targeting transient hardware fault tolerance, leverages significant robustness improvements.

Epipe: A low-cost fault-tolerance technique considering WCET constraints

Transient faults will soon become a critical reliability concern for processors used in mainstream computing. As the mainstream commodity market accepts only low-cost solutions for transient-fault tolerance, traditional high-end solutions are not acceptable due to their prohibitive costs. This paper presents Epipe, a hybrid software/hardware solution that provides sufficient fault coverage with affordable overhead for mainstream commodity systems. Given a program, Epipe identifies its vulnerable instructions (VIs), i.e., the ones that may cause silent data corruptions (SDCs) by compile-time analysis, and selects a subset of VIs to protect considering worst-case execution time (WCET) constraints in the fault-free execution. During program execution on a modified superscalar processor which incurs minimal hardware overhead, Epipe relies on selective instruction replication to handle the VI-induced SDCs and an existing exception detector to tolerate the remaining faults that manifest as system exceptions. Our experimental results show that Epipe provides sufficient fault coverage under some tight WCET constraints and increasingly higher coverage under more relaxed WCET constraints. As the WCET allowance increases from 5% to 15% and then to 25%, the coverage increases from 70.8% to 80% and then to 86.6% averagely. Unlike existing hybrid solutions, Epipe is the first to respect WCET constraints, which are an important concern for real-time systems.

A dual process redundancy approach to transient fault tolerance for ccNUMA architecture

Transient fault is a critical concern in the reliability of microprocessor system. The software fault tolerance is more flexible and lower in cost than the hardware fault tolerance. And also, as architectural trends point toward multicore designs, there is substantial interest in adapting parallel and redundancy hardware resources for transient fault tolerance. The paper proposes a process-level fault tolerance technique, a software-centric approach, which efficiently schedules and synchronizes redundancy processes with ccNUMA processors redundancy. So it can improve efficiency of redundancy processes running and reduce time and space overhead. The paper focuses on the researching of redundancy processes error detection and handling method. A real prototype is implemented that is designed to be transparent to the application. The test results show that the system can timely detect soft errors of CPU and memory that cause the redundancy processes exception, and meanwhile ensure that the services of the application are uninterrupted and delayed shortly.

Applying System Theory to Transient Fault Tolerance and Safety Enhancement of Tunnel Construction Wireless Monitoring and Control System

Transient faults are hard to be detected and located due to their unpredictable nature and short duration, and they are the dominant causations of system failures, which makes it necessary to consider transient fault-tolerant design in the development of modern safety-critical industrial system. In this paper an approach based on system theory is proposed to tolerate the transient faults in tunnel construction wireless monitoring and control systems (TCWMCS), in which the effects of transient faults are expressed by dysfunction of interactions among software applications. After analyzing the dysfunctional interactions of the system by the operational process model and educing the causes of dysfunction in the functional control diagram, a safety enhancement way was proposed for the designers, in which effictive safety constraints were set up to tolerate the transient faults. The experiment evaluation indicated that the effects of transient faults could be exposed by the causal factors of dysfunctional interactions and system safety could be enhanced by the enforcement of appropriate constraints.

PLR: A Software Approach to Transient Fault Tolerance for Multicore Architectures

Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point toward multicore designs, there is substantial interest in adapting such parallel hardware resources for transient fault tolerance. This paper presents process-level redundancy (PLR), a software technique for transient fault tolerance, which leverages multiple cores for low overhead. PLR creates a set of redundant processes per application process and systematically compares the processes to guarantee correct execution. Redundancy at the process level allows the operating system to freely schedule the processes across all available hardware resources. PLR uses a software-centric approach to transient fault tolerance, which shifts the focus from ensuring correct hardware execution to ensuring correct software execution. As a result, many benign faults that do not propagate to affect program correctness can be safely ignored. A real prototype is presented that is designed to be transparent to the application and can run on general-purpose single-threaded programs without modifications to the program, operating system, or underlying hardware. The system is evaluated for fault coverage and performance on a four-way SMP machine and provides improved performance over existing software transient fault tolerance techniques with a 16.9 percent overhead for fault detection on a set of optimized SPEC2000 binaries.

Optimizing Dual-Core Execution for Power Efficiency and Transient-Fault Recovery

Dual-core execution (DCE) is an execution paradigm proposed to utilize chip multiprocessors to improve the performance of single-threaded applications. Previous research has shown that DCE provides a complexity-effective approach to building a highly scalable instruction window and achieves significant latency-hiding capabilities. In this paper, we propose to optimize DCE for power efficiency and/or transient-fault recovery. In DCE, a program is first processed (speculatively) in the front processor and then reexecuted by the back processor. Such reexecution is the key to eliminating the centralized structures that are normally associated with very large instruction windows. In this paper, we exploit the computational redundancy in DCE to improve its reliability and its power efficiency. The main contributions include: 1) DCE-based redundancy checking for transient-fault tolerance and a complexity-effective approach to achieving full redundancy coverage and 2) novel techniques to improve the power/energy efficiency of DCE-based execution paradigms. Our experimental results demonstrate that, with the proposed simple techniques, the optimized DCE can effectively achieve transient-fault tolerance or significant performance enhancement in a power/energy-efficient way. Compared to the original DCE, the optimized DCE has similar speedups (34 percent on average) over single-core processors while reducing the energy overhead from 93 percent to 31 percent.

Defect and Transient Fault-Tolerant System Design for Hybrid CMOS/Nanodevice Digital Memories

Targeting on the future fault-prone hybrid CMOS/nanodevice digital memories, this paper presents two fault-tolerance design approaches that integrally address the tolerance for defects and transient faults. These two approaches share several key features, including the use of a group of Bose-Chaudhuri-Hocquenghem (BCH) codes for both defect tolerance and transient fault tolerance, and integration of BCH code selection and dynamic logical-to-physical address mapping. The first approach is straightforward and easy to implement but suffers from a rapid drop of achievable storage capacity as defect densities and/or transient fault rates increase, while the second approach can achieve much higher storage capacity under high defect densities and/or transient fault rates at the cost of higher implementation complexity and longer memory access latency. Based on extensive computer simulations and BCH decoder circuit design, we have demonstrated the effectiveness of the presented approaches under a wide range of defect densities and transient fault rates, while taking into account of the fault-tolerance storage overhead and BCH decoder implementation cost in CMOS domain

Transient fault-tolerance through algorithms

This article describes that single-version enhanced processing logic or algorithms can be very effective in gaining dependable computing through hardware transient fault tolerance (FT) in an application system. Transients often cause soft errors in a processing system resulting in mission failure. Errors in program flow, instruction codes, and application data are often caused by electrical fast transients. However, firmware and software fixes can have an important role in designing an ESD, or EMP-resistant system and are more cost effective than hardware. This technique is useful for detecting and recovering transient hardware faults or random bit errors in memory while an application is in execution. The proposed single-version software fix is a practical, useful, and economic tool for both offline and online memory scrubbing of an application system without using conventional N versions of software (NVS) and hardware redundancy in an application like a frequency measurement system

MicroThread Based (MTB) coarse grained fault tolerance superscalar processor architecture

Fault tolerance in microprocessor systems has become a popular topic of architecture research. Much work has been done at different levels to accomplish reliability against soft errors, and some fault tolerance architectures have been proposed. But little attention is paid to the thread level superscalar fault tolerance. This letter introduces microthread concept into superscalar processor fault tolerance domain, and puts forward a novel fault tolerance architecture, namely, MicroThread Based (MTB) coarse grained transient fault tolerance superscalar processor architecture, then discusses some detailed implementations.

Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems

Recently, the tradeoff between energy consumption and fault-tolerance in real-time systems has been highlighted. These works have focused on dynamic voltage scaling (DVS) to reduce dynamic energy dissipation and on-time redundancy to achieve transient-fault tolerance. While the time redundancy technique exploits the available slack-time to increase the fault-tolerance by performing recovery executions, DVS exploits slack-time to save energy. Therefore, we believe there is a resource conflict between the time-redundancy technique and DVS. The first aim of this paper is to propose the use of information redundancy to solve this problem. We demonstrate through analytical and experimental studies that it is possible to achieve both higher transient fault-tolerance [tolerance to single event upsets (SEUs)] and less energy using a combination of information and time redundancy when compared with using time redundancy alone. The second aim of this paper is to analyze the interplay of transient-fault tolerance (SEU-tolerance) and adaptive body biasing (ABB) used to reduce static leakage energy, which has not been addressed in previous studies. We show that the same technique (i.e., the combination of time and information redundancy) is applicable to ABB-enabled systems and provides more advantages than time redundancy alone.

A Case for Fault Tolerance and Performance Enhancement Using Chip Multi-Processors

This paper makes a case for using multi-core processors to simultaneously achieve transient-fault tolerance and performance enhancement. Our approach is extended from a recent latency-tolerance proposal, dual-core execution (DCE). In DCE, a program is executed twice in two processors, named the front and back processors. The front processor pre-processes instructions in a very fast yet highly accurate way and the back processor re-executes the instruction stream retired from the front processor. The front processor runs faster as it has no correctness constraints whereas its results, including timely prefetching and prompt branch misprediction resolution, help the back processor make faster progress. In this paper, we propose to entrust the speculative results of the front processor and use them to check the un-speculative results of the back processor. A discrepancy, either due to a transient fault or a mispeculation, is then handled with the existing mispeculation recovery mechanism. In this way, both transient-fault tolerance and performance improvement can be delivered simultaneously with little hardware overhead