Transformer-based Balun Research Articles

A 208–233-GHz Frequency Doubler With 1.1% Power-Added Efficiency in 28-nm CMOS

This letter presents a fully integrated frequency doubler in the TSMC 28-nm CMOS technology. MOS transistor capacitor neutralization is introduced in the differential driving amplifier, which shows better robustness than MOM capacitor neutralization under PVT variations. Besides, a stacked transformer-based balun is designed to achieve good balance performance. The effect of dummy metal on the performance of the proposed balun is also discussed. The measured results show that the 3-dB bandwidth is 25 GHz (208–233 GHz) and the peak power-added efficiency is 1.1% with a dc power consumption of 26.4 mW at 222 GHz. The peak conversion gain is −7.2 dB and the variation in conversion gain is less than 1 dB within −7- to 1-dBm input power range. Moreover, the chip size is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$492\times 412\,\,\mu \text{m}^{2}$ </tex-math></inline-formula> , including GSG and DC pads.

A 300-GHz Transmitter Front End With −4.1-dBm Peak Output Power for Sub-THz Communication Using 130-nm SiGe BiCMOS Technology

This article presents a compact 300-GHz transmitter front end manufactured in a 130-nm SiGe BiCMOS process. The transmitter consists of a 240-GHz amplifier multiplier chain (AMC) and a modified 300-GHz Gilbert mixer. Limited by the space between top two thick metal layers of the SiGe process, the coupling coefficient between the coils, which form a transformer-based balun, is usually small at subterahertz (THz). Therefore, the vertical or horizontal coupling single-turn transformer-based balun will exhibit large insertion loss at around 300 GHz. In this work, a self-shielded Marchand balun (SSMB) with an enhancement to the coupling coefficient is proposed, which is realized by a novel multilayer metal topology with self-shielded coupling (SSC). The AMC is composed of a 120-GHz frequency doubler, a 120-GHz two-stage power amplifier (PA), and a two-way power synthesis balanced frequency doubler. This AMC exhibits a measured peak output power of 5.5 dBm at 252 GHz, with 48-GHz 3-dB bandwidth from 212 to 260 GHz. The transmitter chip achieves a maximum output power of −4.1 dBm at 300 GHz and delivers an output power better than −10 dBm from 270 to 315 GHz. Over the 30-GHz 3-dB bandwidth from 280 to 310 GHz, the transmitter shows a maximum OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> of −6.5 dBm at 296 GHz, a peak conversion gain of −11.2 dB at 298 GHz, and a local oscillator (LO)-to-RF leakage rejection better than 40 dB, with only 300-mW dc power consumption. Compared with other state of the arts, the transmitter exhibits a comparable output power among silicon-based transmitters near 300 GHz.

High-Power V-Band CMOS Frequency Tripler With Efficient Matching Networks

A V-band CMOS frequency tripler with efficient input-output, and interstage matching networks is proposed to improve the output power and conversion efficiency. The interstage matching network, located between a tripler-core and a buffer amplifier, simultaneously performs the impedance matching of a desired third harmonic signal and the filtering of unwanted fundamental and even harmonic signals, without an additional power loss in a small area. Wideband operation and differential signal balance characteristics are achieved at the input and output by using a transformer-based balun with a compensation capacitor. The proposed tripler was implemented in a size of 0.476 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> using the TSMC 65-nm CMOS technology. Measurement results show a saturated output power of 6.4 dBm with a harmonic rejection of 37 dBc for an input power of 10 dBm at 59.4 GHz. The maximum conversion efficiency is 3.92% with an input power of 6.5 dBm at 59.4 GHz.

A −28.5-dB EVM 64-QAM 45-GHz Transceiver for IEEE 802.11aj

This article presents a fully integrated IEEE 802.11aj direct-conversion transceiver system in a 120-nm SiGe:C BiCMOS technology. The system includes a transmitter, a receiver, and two onboard substrates integrated waveguide-fed Yagi-Uda antennas. In the millimeter-wave frequency band, the common-mode (CM) signal in a transformer-based balun is a limiting factor for the linearity of differential devices. In this work, we analyze the cause of the CM effect and provide fast impedance equalization with a passive component compensation method to resolve this problem, which improves the linearity of the transmitter. A <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T$ </tex-math></inline-formula> -type second-order harmonic termination method is applied at the power amplifier (PA) output to further improve the linearity of the transmitter. The self-mixing method-based power detector is adopted at the output of the transmitter to have an accurate image signal and local oscillator (LO) leakage calibration. The transmitter reaches an output 1-dB compression point (OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> ) of 14.6–16.4 dBm and a conversion gain (CG) higher than 24 dB in the IEEE 802.11aj frequency band, operating from 42.3 to 48.4 GHz. The receiver achieves a 3.8–4.1-dB noise figure, −18.7- to −22-dBm input 1-dB compression point, and a CG better than 43.8 dB in the IEEE 802.11aj frequency band. In the system wireless data transmission test, the transceiver is fully compliant with the error vector magnitude (EVM) requirement of the IEEE 802.11aj standard up to the 64-quadrature amplitude modulation (QAM) operating mode, and the measured transmitter-to-receiver EVM is better than −28.5 dB at a 1-m distance over the IEEE 802.11aj frequency band. Compared to other states of the art, the transmitter’s OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> is the highest, and the demonstrated transceiver system delivers the highest performance in the IEEE 802.11aj wireless link.

A 250-GHz Differential SiGe Amplifier With 21.5-dB Gain for Sub-THz Transmitters

This article presents a 250-GHz SiGe amplifier composed of three differential cascode stages in a 0.13- μ m SiGe BiCMOS technology ( f T/ f MAX = 300/500 GHz). The Marchand balun is utilized to implement single-ended to differential signal transformation for its superior performance over the transformer-based balun at sub-THz frequencies, which has been investigated and verified through electromagnetic (EM) simulations. A stair-like interconnection method and conventional positive feedback technique are used to improve the inherent gain of the active device. The proposed amplifier exhibits a record S21 of 21.5 dB at 252 GHz and a 3-dB bandwidth of 11 GHz with the capability of gain control. The measured OP 1dB is −3.7 dBm with the corresponding power added efficiency (PAE) of 0.3%, and the saturated output power is estimated to exceed 0 dBm at 252 GHz. The overall power consumption of the chip is 149 mW. Along with remarkable gain and output power, the compact amplifier is suitable to be adopted as an output block in the sub-THz transmitters.

A Coupler-Based Differential mm-Wave Doherty Power Amplifier With Impedance Inverting and Scaling Baluns

Designing Doherty power amplifiers (PAs) at high millimeter-wave (mm-Wave) range remains a major challenge because most Doherty combiners at this frequency band are inefficient. To resolve this bottleneck, we analyze balun response under load variation and subsequently propose the Doherty PA architecture with impedance inverting and scaling baluns that perform active load modulation on differential PAs and delivers combined power to a single-ended load. At the PA output/input stage, instead of utilizing the transformer-based balun commonly used at RF and low mm-Wave frequencies, we explore the coupler-based balun to resonate out the device parasitic capacitance and achieve well-balanced differential to single-ended conversion at high mm-Wave frequencies. Based on the coupled-line theory and our analysis, we derive the [Y] matrix of the coupler-based balun and originate various solutions for baluns that can invert or scale impedance. From this derivation, we conceive a canonical form of impedance inverting baluns when the electrical length of coupled lines equals 45°. We also propose a close-formed solution for the coupler-based impedance scaling balun that is electrically equivalent to an idealistic transformer in series with a small inductance. We then combine the proposed impedance inverting and scaling balun structures to construct a Doherty network that exhibits desirable Doherty active load modulation and occupies a single-transformer footprint. On the active circuit design, we employ the adaptive biasing circuit for both driver and PA stages of the auxiliary PA to enhance the main and auxiliary cooperation. Using a 45-nm GlobalFoundries CMOS SOI process, we fabricate a proof-of-concept Doherty PA that demonstrates 20.1-dBm $P_{\mathrm {sat}}$ , 19.3dBm OP1,dB, 26% peak power-added efficiency (PAE), and 16.6% PAE at 7-dB power back-off (PBO) from OP1 dB at 60 GHz. Our results indicate a substantial PAE enhancement at PBO and a state-of-the-art modulation efficiency achieved when transmitting digital pre-distortion (DPD)-free 64-QAM-modulated signals.

A 3.15-mW +16.0-dBm IIP3 22-dB CG Inductively Source Degenerated Balun-LNA Mixer With Integrated Transformer-Based Gate Inductor and IM2 Injection Technique

This article proposes two linearization techniques in improving the third-order input intercept point (IIP3) of a balun-low-noise amplifier (LNA) mixer. First, the intrinsic third-order intermodulation (IM3) product of the inductively source degenerated (ISD) transconductor from the second-order derivative transconductance component ( ${g}''_{m}$ ) is reduced by tailoring toward the optimum biasing point at the moderate-inversion region. Second, the generated IM3 current by the first-order derivative transconductance ( ${g}'_{m}$ ) due to the interaction with the feedback component in the ISD transconductor is attenuated by second-harmonic injection via the bulk of the ISD transconductor. Furthermore, a transformer-based gate inductor and a transformer-based balun are applied to improve the input impedance matching and produce a balanced differential input signal. Measured results in 0.13- $\mu \text{m}$ CMOS show a high IIP3 of +16 dBm and a conversion gain (CG) of 22 dB at 2.4 GHz. The double-sideband (DSB) noise figure (NF) is 7.2 dB, and the power consumption is 3.15 mW at 1.2 V.

A 19.5% Efficiency 51–73-GHz High-Output Power Frequency Doubler in 65-nm CMOS

This letter presents a 51–73-GHz high-output power and efficiency frequency doubler, which is fabricated in a standard 65-nm CMOS process. The proposed frequency doubler adopts a fourth-order transformer-based balun and a dual- LC tank network to achieve wideband operating at input and output ports. In addition, a common-source amplifier with a Gm-boosting technique is used as an output buffer to improve the output power and efficiency. The measured results show that the doubler achieves input and output return losses below −10 dB from 26 to 36 GHz and 53 to 80 GHz, respectively. The measured maximum gain is 0.8 dB at 66 GHz with 22-GHz 3-dB gain bandwidth at an input power of 1 dBm. Furthermore, with an input power of 7 dBm, the proposed doubler also exhibits a high efficiency of 19.5% and an output power of 5.7 dBm at 66 GHz. The dc power consumption is 14 mW with 1-V power supply, and the chip size is $0.63\times0.52$ mm2 including all test pads.

A Compact 5 GHz Power Amplifier Using a Spiral Transformer for Enhanced Power Supply Rejection in 180-nm CMOS Technology

We present a compact 5 GHz, class A power amplifier (PA) applicable for a wireless combo-chip that supports multiple radio systems in 180 nm CMOS technology. The proposed two-stage linear PA consists of a cascode input stage with a transformer-based balun, combined with a balancing capacitor as the load, where the single-ended signal is converted into the balanced output and a second-stage, class A push–pull amplifier with another transformer-based balun, which efficiently combines the output power differentially to drive a single-ended 50 Ω load. The proposed single-ended PA with an internal balanced configuration can achieve a power supply rejection ratio of 9.5 to 65.9 dB at 0.1 to 3.5 GHz, which is around a 12 to 37 dB improvement compared to a conventional single-ended PA with the same power gain. The results show that the proposed PA has a gain of 15.5 dB, an output-referred 1 dB gain compression point of 13 dBm, an output intercept point of 22 dBm with a 5 MHz frequency offset, an output saturated power of 15.4 dBm, and a peak power-added efficiency of 15%. The implemented PA consumes a DC current of 72 mA under 1.8 V supply. The core chip size is 0.65 mm2 without pads.

A Wideband SiGe BiCMOS Frequency Doubler With 6.5-dBm Peak Output Power for Millimeter-Wave Signal Sources

This paper presents a balanced frequency doubler with 6.5-dBm peak output power at 204 GHz in 130-nm SiGe BiCMOS technology ( f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> /f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> = 210/250 GHz). To convert the single-ended input signal to a differential signal for balanced operation, an on-chip transformer-based balun is employed. Detailed design procedure and compensation techniques to lower the imbalance at the output ports, based on mixed mode S parameters are proposed and verified analytically and through electromagnetic simulations. The use of optimized harmonic reflectors at the input port results in a 2-dBm increase in output power without sacrificing the bandwidth of interest. The measured conversion loss of the frequency doubler is 9 dB with 6-dBm input power at 204-GHz output. The measured peak output power is 6.5 dBm with an on-chip power amplifier stage. The 3-dB output power bandwidth is measured to be wider than 50 GHz (170-220 GHz). The total chip area of the doubler is 0.09 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the dc power consumption is 90 mW from a 1.8-V supply, which corresponds to a 5% collector efficiency.

10 to 40 GHz Superheterodyne Receiver Frontend in 0.13 µm SiGe BiCMOS Technology

AbstractA fully integrated 10–40 GHz superheterodyne receiver frontend using a 40–46 GHz IF is presented. The frontend consists of a differential low noise amplifier, a fully differential mixer, a single-ended frequency quadrupler and a transformer-based balun followed by an amplifier to convert the quadrupler’s single-ended output to a differential signal to drive the LO port of the mixer. The circuit is designed and fabricated in a 250 GHz

A High Efficiency E-Band CMOS Frequency Doubler With a Compensated Transformer-Based Balun for Matching Enhancement

This letter presents a broadband high efficiency frequency doubler based on a new and effective compensation technique. A transformer based input balun achieves good balanced performance and input matching by the newly invented central capacitor based compensation technique. It demonstrates a peak conversion gain (CG) of $-$ 2.5 dB and peak efficiency of 9.7% with a saturated output power of 2.5 dBm at 74 GHz. The doubler exhibits a 3 dB CG bandwidth of 28 GHz from 62 to 90 GHz. The fundamental rejection is larger than 20 dB. The doubler is fabricated in a 65 nm CMOS technology with chip area of $0.6\times 0.45 {\rm mm}^{2}$ and consumes 9–14 mW power.

Co-design of a wideband double-balanced active mixer and transformer-based baluns for 77 GHz radar applications

This paper presents a 130-nm BiCMOS active mixer dedicated to 77GHz automotive radar applications. The architecture is based on a double-balanced Gilbert cell with integrated transformer-based baluns. Interconnections between devices, capacitor accesses and Tee-junctions are modeled using EM software in order to improve the simulation accuracy. Focusing on wideband operation, the transformer-based baluns are considered as part of the input matching network. Sizing of the transformer is detailed along with its amplitude and phase balance performances. The design of the input matching circuit integrating the transformer is presented, providing a 12-GHz bandwidth. Measured noise figure, conversion gain and compression point of the mixer are displayed and compared to the state of the art.

93–133 GHz Band InP High-Electron-Mobility Transistor Amplifier with Gain-Enhanced Topology

In this study, we developed a new type of high-frequency amplifier topology using 75-nm-gate-length InP-based high-electron-mobility transistors (InP HEMTs). To enhance the gain for a wide frequency range, a common-source common-gate hybrid amplifier topology was proposed. A transformer-based balun placed at the input of the amplifier generates differential signals, which are fed to the gate and source terminals of the transistor. The amplified signal is outputted at the drain node. The simulation results show that the hybrid topology exhibits a higher gain from 90 to 140 GHz than that of the conventional common-source or common-gate amplifier. The two-stage amplifier fabricated using the topology exhibits a small signal gain of 12 dB and a 3-dB bandwidth of 40 GHz (93–133 GHz), which is the largest bandwidth and the second highest gain reported among those of published 120-GHz-band amplifiers. In addition, the measured noise figure was 5 dB from 90 to 100 GHz.

An ultra low power consumption millimeter-wave voltage controlled oscillator in a 65 nm CMOS-SOI technology

This paper presents an ultra low power consumption 65 GHz LC-VCO dedicated to wireless high data rate applications. It is designed in a 65 nm CMOS SOI process, which improves passive devices behavior. The proposed VCO achieves a frequency tuning range (FTR) of 9.7 % and a phase noise of ?110.86 dBc/Hz at 10 MHz of the carrier. All integrated passive components (including transmission lines and a transformer-based balun) are modeled using advanced electromagnetic (EM) field solvers. The power consumption of the proposed VCO is as low as 1.1 mW when biased by a 0.8-V supply voltage. The FoM of this millimeter wave circuit, whose core occupies a silicon footprint of only 0.047 mm2, is ?184.07 dBc/Hz.