Thin-film Transistors Transfer Research Articles

Artificial Q-Grader: Machine Learning-Enabled Intelligent Olfactory and Gustatory Sensing System.

Portable and personalized artificial intelligence (AI)-driven sensors mimicking human olfactory and gustatory systems have immense potential for the large-scale deployment and autonomous monitoring systems of Internet of Things (IoT) devices. In this study, an artificial Q-grader comprising surface-engineered zinc oxide (ZnO) thin films is developed as the artificial nose, tongue, and AI-based statistical data analysis as the artificial brain for identifying both aroma and flavor chemicals in coffee beans. A poly(vinylidene fluoride-co-hexafluoropropylene)/ZnO thin film transistor (TFT)-based liquid sensor is the artificial tongue, and an Au, Ag, or Pd nanoparticles/ZnO nanohybrid gas sensor is the artificial nose. In order to classify the flavor of coffee beans (acetic acid (sourness), ethyl butyrate and 2-furanmethanol (sweetness), caffeine (bitterness)) and the origin of coffee beans (Papua New Guinea, Brazil, Ethiopia, and Colombia-decaffeine), rational combination of TFT transfer and dynamic response curves capture the liquids and gases-dependent electrical transport behavior and principal component analysis (PCA)-assisted machine learning (ML) is implemented. A PCA-assisted ML model distinguished the four target flavors with >92% prediction accuracy. ML-based regression model predicts the flavor chemical concentrations with >99% accuracy. Also, the classification model successfully distinguished four different types of coffee-bean with 100% accuracy.

A Study about Schottky Barrier Height and Ideality Factor in Thin Film Transistors with Metal/Zinc Oxide Nanoparticles Structures Aiming Flexible Electronics Application.

Zinc oxide nanoparticles (ZnO NP) used for the channel region in inverted coplanar setup in Thin Film Transistors (TFT) were the focus of this study. The regions between the source electrode and the ZnO NP and the drain electrode were under investigation as they produce a Schottky barrier in metal-semiconductor interfaces. A more general Thermionic emission theory must be evaluated: one that considers both metal/semiconductor interfaces (MSM structures). Aluminum, gold, and nickel were used as metallization layers for source and drain electrodes. An organic-inorganic nanocomposite was used as a gate dielectric. The TFTs transfer and output characteristics curves were extracted, and a numerical computational program was used for fitting the data; hence information about Schottky Barrier Height (SBH) and ideality factors for each TFT could be estimated. The nickel metallization appears with the lowest SBH among the metals investigated. For this metal and for higher drain-to-source voltages, the SBH tended to converge to some value around 0.3 eV. The developed fitting method showed good fitting accuracy even when the metallization produced different SBH in each metal-semiconductor interface, as was the case for gold metallization. The Schottky effect is also present and was studied when the drain-to-source voltages and/or the gate voltage were increased.

Low-temperature formation of high-mobility a-InGaZnOx films using plasma-enhanced reactive processes

This work demonstrated the low-temperature fabrication of high-mobility a-InGaZnOx (a-IGZO) films using plasma-enhanced reactive processing. The effect of the post-processing temperature on the performance of IGZO thin-film transistors (TFTs) using these a-IGZO films as a channel layer was also investigated. IGZO TFTs incorporating a-IGZO films plasma-treated at temperatures as low as 200 °C exhibited the expected TFT transfer characteristics, with field effect mobility values as high as 40 cm2 V−1 s−1. The fabrication of IGZO TFTs that exhibited homogeneous characteristics over large substrate areas was attempted, by assessing the effects of the plasma treatment on a-IGZO films deposited at various oxygen flow rate ratios. The electrical properties of IGZO TFTs using plasma-treated films were found to be dramatically improved, irrespective of the film deposition conditions prior to the plasma treatment. These results confirm the feasibility of producing IGZO TFTs with uniform characteristics over large substrates areas.

Test System for Thin Film Transistor Parameter Extraction in Active Matrix Backplanes

Thin film transistor (TFT) active matrix backplanes are used in large area electronic systems, such as displays and image sensors. With backplanes being fabricated on wearable and flexible substrates, the possibilities of operational faults in backplanes have increased. These faults could either be hard faults, such as line opens or shorts or could be softer faults, such as time dependent variations in the TFT transfer characteristics. Real time diagnosis of these faults require built-in-self-test systems. While many such systems have been demonstrated to diagnose hard faults, an easily realizable system to identify soft faults, such as variations in transistor transconductance remain an open challenge. In this paper, we discuss a system that extracts the transconductance by charging and then discharging the pixel capacitor at various gate voltages for an active matrix liquid crystal display backplane. This permits a plot of the time averaged current versus the gate voltage from which the spatial variation of transconductance can be extracted. The details of the design are discussed and a proof of concept with a $3\times 4$ amorphous silicon backplane is demonstrated.

Bending Stress Induced Performance Change in Plastic Oxide Thin-Film Transistor and Recovery by Annealing at 300 °C

We report the effect of repeated tensile bending on the performance of amorphous indium-gallium- zinc oxide (a-IGZO) thin-film transistors (TFTs) on 15-μm polyimide substrate. Bending direction is vertical or parallel to the current path in a-IGZO TFT. With increasing bending time, the transfer curve shifts to the negative gate voltage direction. It is noted that the shift is smaller for longer channel length TFT. We performed technology computer aided design simulation for the TFT transfer curves and found that donorlike and acceptorlike states increase, respectively,by 2.5×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">17</sup> and 0.4×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">17</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> after 10k bending. The recovery of the transfer curve is studied by thermal annealing of the stressed TFT as a variation of annealing temperature and it is found that the performance can be completely recovered by thermal annealing at 300 °C for 1 h.

Oxide Thin-Film Transistors on Fibers for Smart Textiles

Smart textiles promise to have a significant impact on future wearable devices. Among the different approaches to combine electronic functionality and fabrics, the fabrication of active fibers results in the most unobtrusive integration and optimal compatibility between electronics and textile manufacturing equipment. The fabrication of electronic devices, in particular transistors on heavily curved, temperature sensitive, and rough textiles fibers is not easily achievable using standard clean room technologies. Hence, we evaluated different fabrication techniques and multiple fibers made from polymers, cotton, metal and glass exhibiting diameters down to 125 μm. The benchmarked techniques include the direct fabrication of thin-film structures using a low temperature shadow mask process, and the transfer of thin-film transistors (TFTs) fabricated on a thin (≈1 μm) flexible polymer membrane. Both approaches enable the fabrication of working devices, in particular the transfer method results in fully functional transistor fibers, with an on-off current ratio &gt; 10 7 , a threshold voltage of ≈0.8 V , and a field effect mobility exceeding 7 c m 2 V − 1 s − 1 . Finally, the most promising fabrication approach is used to integrate a commercial nylon fiber functionalized with InGaZnO TFTs into a woven textile.

(Invited) Instability Mechanisms in Amorphous Oxide Semiconductors Leading to a Threshold Voltage Shift in Thin Film Transistors

Amorphous indium gallium zinc oxide (a-IGZO) has been successfully employed commercially as the channel layer in thin film transistors (TFTs) for active-matrix flat panel displays. However, these TFTs are known to suffer from a threshold voltage shift upon application of a gate bias. The threshold voltage shift is reversible through annealing. A similar phenomenon is observed in other TFTs with an amorphous oxide semiconductor channel. The migration of oxygen vacancies is proposed as being the microscopic mechanism causing this effect as it can lead to a change in the equilibrium distribution of defect states in the band gap of the semiconductor. This would manifest itself as a reversible threshold voltage shift in the TFT transfer characteristics, as observed experimentally.

Non-ideal current drop behavior in ultra-thin inorganic a-InGaZnO thin film transistors

Recent research in flexible and imperceptible electronic devices has been dominated by the development of robust channel materials and adequate processes for thin-film transistors (TFTs) based on an inorganic amorphous oxide. Water-soluble sacrificial polyvinyl alcohol and parylene were employed for the fabrication of ultra-light amorphous In–Ga–Zn–O (a-IGZO) TFTs with a top-gate configuration. But, a higher negative gate bias stress (≥5 V) caused anomalous degradation in the on-current level and field-effect mobility with increasing stress time, which was attributed to the rough surface of the chemical vapor deposited parylene film. The current work adopts an ultraviolet ozone irradiation treatment for improving the surface roughness of the polymer films prior to the fabrication of oxide TFTs. A suppression of the on-current drop and typical TFTs transfer behavior were observed under light irradiation with a negative gate bias stress. The a-IGZO TFTs on the parylene surface treated for 20 min exhibited a device thickness of approximately 5 µm and good TFT performances with field-effect mobility, subthreshold swing, and on/off current ratio values of 13.9 cm2/V s, 0.24 V/dec, and 7 × 108, respectively. This survey suggests that a polymer film with a smooth surface can play a beneficial role in fabricating flexible ultra-slim a-IGZO TFTs.

Extremely Sensitive Dependence of SnOx Film Properties on Sputtering Power.

An extremely sensitive dependence of the electronic properties of SnOx film on sputtering deposition power is discovered experimentally. The carrier transport sharply switches from n-type to p-type when the sputtering power increases by less than 2%. The best n-type carrier transport behavior is observed in thin-film transistors (TFTs) produced at a sputtering power just below a critical value (120 W). In contrast, at just above the critical sputtering power, the p-type behavior is found to be the best with the TFTs showing the highest on/off ratio of 1.79 × 104 and the best subthreshold swing among all the sputtering powers that we have tested. A further increase in the sputtering power by only a few percent results in a drastic drop in on/off ratio by more than one order of magnitude. Scanning electron micrographs, x-ray diffraction spectra, x-ray photoelectron spectroscopy, as well as TFT output and transfer characteristics are analyzed. Our studies suggest that the sputtering power critically affects the stoichiometry of the SnOx film.

Dual electrical behavior of multivalent metal cation-based oxide and its application to thin-film transistors with high mobility and excellent photobias stability.

The effect of multivalent metal cations, including vanadium(V) and tin (Sn), on the electrical properties of vanadium-doped zinc tin oxide (VZTO) was investigated in the context of the fabrication of thin-film transistors (TFTs) using a single VZTO film and VZTO/ZTO bilayer as channel layers. The single VZTO TFT did not show any response to the gate voltage (insulator-like behavior). On the other hand, the VZTO/ZTO bilayer TFT exhibited a typical TFT transfer characteristic (semiconducting behavior). X-ray photoelectron spectroscopy revealed that, in contrast to what is commonly true in many oxides, oxygen vacancies (V(O)) in VZTO did not provide a dominant contribution to the total carrier concentration, because the V(O) peak area in the single VZTO film was 5.4% and reduced to 4.5% in VZTO/ZTO bilayer. Instead, Sn 3d5/2 and V 2p3/2 spectra suggest that the significant reduction in Sn and V ions is strongly related to the insulator-like behavior of the VZTO film. In negative-bias illumination tests and illumination tests with various photon energies, the VZTO/ZTO bilayer TFT had much better stability than the ZTO TFT. This result is attributed to the reduction of donor-like states ([Formula: see text]O) that can be positively ionized by blue and green illumination.

Correlation between nano-scale microstructural behavior and the performance of ZnO thin-film transistors.

Binary ZnO active layers possessing a polycrystalline structure were deposited with various argon/oxygen flow ratios at 250 degrees C via sputtering. Then ZnO thin-film-transistors (TFTs) were fabricated without additional thermal treatments. As the oxygen content increased during the deposition, the preferred orientation along the (0002) was weakened and the rotation of the grains increased, and furthermore, less conducting films were observed. On the other hand, the reduced oxygen flow rate induced the formation of amorphous-like transition layers during the initial growth due to a high growth rate and high energetic bombardment of the adatoms. As a result, the amorphous phases at the gate dielectric/channel interface were responsible for the formation of a hump shape in the subthreshold region of the TFT transfer curve. In addition, the relationship between the crystal properties and the shift in the threshold voltage was experimentally confirmed by a hysteresis test.

Role of oxygen vacancies on the bias illumination stress stability of solution-processed zinc tin oxide thin film transistors

Solution-processed ultra-thin (∼3 nm) zinc tin oxide (ZTO) thin film transistors (TFTs) with a mobility of 8 cm2/Vs are obtained with post spin-coating annealing at only 350 °C. The effect of light illumination (at wavelengths of 405 nm or 532 nm) on the stability of TFT transfer characteristics under various gate bias stress conditions (zero, positive, and negative) is investigated. It is found that the ΔVth (Vthstress 3400 s − stress 0 s) window is significantly positive when ZTO TFTs are under positive bias stress (PBS, ΔVth = 9.98 V) and positive bias illumination stress (λ = 405 nm and ΔVth = 6.96 V), but ΔVth is slightly negative under only light illumination stress (λ = 405 nm and ΔVth = −2.02 V) or negative bias stress (ΔVth = −2.27 V). However, the ΔVth of ZTO TFT under negative bias illumination stress is substantial, and it will efficiently recover the ΔVth caused by PBS. The result is attributed to the photo-ionization and subsequent transition of electronic states of oxygen vacancies (i.e., Vo, Vo+, and Vo++) in ZTO. A detailed mechanism is discussed to better understand the bias stress stability of solution processed ZTO TFTs.

Role of the crystallinity of ZnO films in the electrical properties of bottom-gate thin film transistors

The strong correlation between the microstructural characteristics of ZnO channel layers grown at various temperatures by radio-frequency magnetron sputtering and the electrical performances of resulting bottom-gate thin film transistors (TFTs) was reported. Transmission electron microscopy revealed that increasing growth temperature enhanced degree of c-axis preferred orientation and enlarged width of columns in the ZnO films. The ZnO channel layers grown at 250 and 350 °C exhibited TFT saturation behavior. However, growing them at ≥ 350 °C produced small grains in the junctions of ZnO/SiO 2 interface and grain boundaries, which led to hump behavior in TFT transfer curve caused by formation of additional boundaries.

Reduction of Hot Carrier Effects in Silicon-on-Glass TFTs

Hot carrier (HC) instability of thin-film transistors (TFTs) fabricated on single-crystal,silicon-on-glass (SiOG) substrates is studied. The formation of the SiOG substrate is achieved by the transfer of a single-crystal silicon film to a display-glass substrate. The transfer process creates an in-situ barrier layer free of mobile ions in the glass adjacent the silicon film. The n- and p-channel TFT transfer characteristics typically exhibit excellent on-state performance with gate voltage swing values of 180 mV/decade, electron and hole mobilities of ∼ 251 and 201 cm2/V·s respectively, and threshold voltages of approximately −0.3 and −1.2 V for the n- and p-channel TFT’s respectively. While p-channel TFTs exhibit good stability, on-current degradation is observed in the transfer characteristics of the n-channel TFT. The degradation is due to HC stress. In this study, the integration of a lightly doped drain (LDD) structure in the n-channel SiOG TFTs to minimize HC instability is reported. The LDD design incorporates 2 μm offset regions. The offset regions are lightly doped (n-) with phosphorus ions implanted at 10 keV. N-levels of ∼ 1 × 1013, 2 × 1013, and 3 × 1013 cm−2 are analyzed to determine the optimum doping conditions that reduce HC instability while minimizing degradation in the on-state device performance.

BIAS STRESS AND MEASUREMENT OF CHARACTERISTICS OF HYDROGENATED AMORPHOUS-SILICON THIN FILM TRANSISTORS USING ALTERNATING CURRENT DRIVING PULSE

A thin film transistor (TFT) characteristics measuring and bias stress applying system using an alternating current (AC) pulse sequence similar to a real driving pulse was developed to study the properties of hydrogenated amorphous-silicon (a-Si:H) TFTs under real operating conditions. Using this system, the application of a gate bias stress and the measurement of source-to-drain current were performed successfully. Degradation of the TFT transfer curve depended on the ratio of on time to off time for a fixed on time; a longer off time made the shift of threshold voltage V TH smaller. In addition, degradation of transfer curves depended on the frequency of the driving pulse; a higher frequency pulse produced a larger degradation. These results could originate from the dependence of the direction of V TH shift on the polarity of the gate bias, and the differences of injection barrier height and the mobility of the electron and hole. Using the AC driving pulse and the transient measurement system proposed in this study may be useful in understanding the response of TFTs under real operating conditions.

Reduction of Hot Carrier Effects in Corning Silicon-on-Glass TFTs

Hot carrier (HC) instability of thin film transistors (TFTs) fabricated on single crystalline Corning® Silicon-on-Glass (SiOG) substrates is studied (1). The n- and p-channel TFT transfer characteristics typically exhibit excellent on-state performance with electron and hole field effect mobilities (μfe) of ~251 and 201 cm2/V⋅s, threshold voltages of ~-0.3 and -1.2 V, and gate swing (S) values of ~180 mV/dec. While p-channel TFTs exhibit good stability, on-current (ION) degradation is unfortunately observed in the transfer characteristics of the n-channel TFT due to HC stress. In this study, the integration of a lightly doped drain (LDD) structure to minimize HC instability in the n-channel SiOG TFTs is reported. The LDD design has 2 μm regions produced by ion implanting phosphorus at 10 keV to a light doping (n-) level. N- levels of ~1 × 1013, 2 × 1013, and 3 × 1013 cm−2 are analyzed to determine the optimum doping conditions that leads to HC improvement with minimal detrimental impact to the on-state device performance.

Development of rollable silicon thin‐film‐transistor backplanes utilizing a roll‐to‐roll continuous lamination process

Abstract— Rollable silicon thin‐film‐transistor (TFT) backplanes utilizing a roll‐to‐roll process have been developed. The roll‐to‐roll TFT‐backplane technology is characterized by a glass‐etching TFT transfer process and a roll‐to‐roll continuous lamination process. The transfer process includes high‐rate, uniform glass‐etching to transfer TFT arrays fabricated on a glass substrate to a flexible plastic film. In the roll‐to‐roll process, thinned TFT‐glass sheets (0.1 mm) and a base‐film roll are continuously laminated using a permanent adhesive. Choosing both an appropriate elastic modulus for the adhesive and an appropriate tension strength to be used in the process is the key to suppressing deformation of the TFT‐backplane rolls caused by thermal stress. TFT backplanes that can be wound, without any major physical damage such as cracking, on a roll whose core diameter is approximately 300 mm have been sucessfully obtained. Incorporating the TFT‐backplane rolls into other roll components, such as color‐filter rolls, will make it possible to produce TFT‐LCDs in a fully roll‐to‐roll manufacturing process.

Reduction of Off-State Currents in Silicon on Glass Thin Film Transistor by Off-State Bias Stress

We have studied the impact of off-bias stress on the performance of thin film transistors (TFTs) fabricated on single crystalline silicon-on-glass substrates. The p-channel TFT transfer characteristics typically exhibit excellent on-state performance with a field-effect mobility of 203 cm 2 /V s and a subthreshold swing of around 200 mV/dec. However, the off-state drain current has increased with increasing gate voltage. This increasing off-state current phenomenon can be significantly reduced by performing an off-state bias for 10 s. The formation of electron traps in the gate oxide near the drain is the main factor that reduces the off-state leakage current.

Nonvolatile memory based on sol-gel ZnO thin-film transistors with Ag nanoparticles embedded in the ZnO/gate insulator interface

A nonvolatile memory is demonstrated using a solution-processed sol-gel ZnO thin-film transistor (TFT) in which Ag nanoparticles are embedded as charge storage nodes at the insulator-ZnO interface. Its TFT transfer characteristics exhibit a large clockwise hysteresis that is proportional to the gate bias sweep range. Measurement of the threshold voltage shift versus the pulse width of gate bias reveals that the device can be programed or erased at a time scale of as short as 10−4 s. Retention of the initial memory window is measured to be 27% after 105 s and projected to last until 107 s.

Self-aligned Thin Film Transistor Fabrication with an Ultra Low Temperature Polycrystalline Silicon Process on a Benzocyclobutene Planarized Stainless Steel Foil Substrate

AbstractCompared to plastic, from the view point of ultra low temperature poly-Si (ULTPS) processes for realizing flexible active matrix organic light emitting diode (AM-OLED) display, SSF offers high thermal resistance and chemical stability, and lithography stability. As SSF is stiffer than plastic film, SSF is expected to reduce stress which originates from difference in coefficient of thermal expansion. However, SSF substrate itself also bears surface roughness problem, which necessitates an appropriate planarization step. Also to fully integrate both the drive circuits and the pixel thin-film transistor(TFT)s in a monolithic complementary metal-oxide-semiconductor (CMOS) technology high mobility is required, calling for poly-Si usage.We will deal with the planarization process, and then address various processing issues. Especially, we will demonstrate our successful SLS of Si on SSF substrates. Finally we show the device performances. All fabrication temperatures were kept below 200 oC to meet a ULTPS process.Due to the rolling process for manufacturing foils, the SSF surface is rough. We have measured average roughness of 500 nm, respectively. With benzocyclobutene (BCB), we have successfully planarized the surface with average roughness was less than 0.5 nm.Our TFT's active layer was obtained by laser crystallizing amorphous Si (a-Si) films. To obtain a high quality gate dielectric film, we formed a SiO2 film using an O2 plasma treatment on the surface of the poly-Si film and then deposited Al2O3 film by plasma enhanced atomic layer deposition. Then gate metal was deposited and patterned. Source and drain regions were p+ doped by ion implantation to form a self-aligned gate structure. We have used SiNx film as interlayer dielectrics.Briefly we discuss a practical approach for realizing SLS on a SiO2 buffer. The Si-on-SiO2 layer stacking is energetically unstable. Should have not controlled the heat during laser crystallization, liquid Si would recede to expose the SiO2 layer. Dewetting is suppressed by adjusting the buffer density, and densifying the a-Si film. To implement the SLS, we have optimally conjugated the densities of the buffer film and the a-Si film to produce Si grains with sizes of ~6 ¥ìm on a BCB planarized SSF.Our p-channel TFT transfer performance exhibits a field effect mobility (¥ì) of 95 cm2/Vs, a threshold voltage (Vt) of -3 V and a sub-threshold swing(S-S) of 0.5 V/dec.. The off-current level is ~ 10 pA at drain voltage (Vd) of -1V and the Ion/Ioff is 106 . Especially our stable Vt consents to the electrical stability for driving displays. This feature might be attributed to the improved interface between the active layer and the gate dielectrics by plasma oxidation.