Transconductance Characteristics Research Articles

A plant based electrochemical device with transistor like behavior

Since its invention, transistor has become the fundamental building block of virtually all of today’s integrated circuits which constitute the electronics technology. In the present letter, we report the vegetal version of a self-powered electrochemical transistor, i.e., a device with an inherent energy source which exhibits energy-converting and amplifying-modulating properties. Surprisingly, at the interface constituted by the surface of an n-type germanium sample and a vegetal slice it become apparent that the surface of the n-type germanium passing anodic current acts as a multiplying collector for holes. Experimental transconductance characteristics show well-defined the cut-off, active and saturation regions. Likewise, since the collector is itself part of an electrolytic cell, device incorporates its own power supply. Thereby, it is able to reproduce an analogical AC signal via the DC electrolytic cell voltage. Furthermore, one of the most outstanding properties of the transistors is their DC current gain (hFE), which for commercially available small-signal transistors typically ranges 50–350, and for medium power transistors 15–70. The proposed device presents an hFE of 70 and 40 for the potato and apple based transistors respectively. Genuinely, this approach opens an alternative route for the development of a novel green electronics based on self-powered vegetative devices. Genuinely, this approach opens an alternative route for the development of a novel green electronics based on self-powered vegetative devices which could works as sensing devices for monitoring living plants during sow and harvest.

60Co gamma radiation effects on NPN transistor at cryogenic temperature.

The 60Co gamma radiation effects on the DC electrical characteristics of silicon NPN transistor were studied in the dose range of 100krad to 6Mrad at room temperature (300K) and cryogenic temperature (77K). The measurements were carried out at both 300 and 77K temperature. The electrical characteristics such as Gummel characteristics, excess base current (ΔIB), current gain (hFE), transconductance (gm) and output characteristics were studied in situ as a function of total dose. The results show that there is a considerable degradation in the electrical parameters of the device irradiated both at 300 and 77K as a consequence of increase in excess base current (ΔIB) because of the formation of generation and recombination centers in the emitter-base spacer oxide (SiO2). At cryogenic temperature irradiation, the degradation in electrical characteristics is less because of the physical phenomena such as carrier freezeout effect, decreased recombination rate, reduced charge yield, decreased electron mobility, etc.

Capacitance modeling, simulation and RF characterization of horizontal floating gate field effect transistor (H-FGFET) for gas sensing application

In this paper, physics-based capacitance model has been developed for horizontal floating gate field effect transistor (H-FGFET). The horizontal design of floating gate (FG) FET allows detection of large gas molecules like nitrogen dioxide (NO2), sulphur dioxide (SO2), hydrogen sulfide (H2S), carbon dioxide (CO2) etc. In order to validate the proposed model, the device has been designed using Sentaurus TCAD simulator and results have been validated with experimental data. Different electrical parameters such as transfer characteristics, switching ratio, output characteristics, threshold voltage, drain induced barrier lowering (DIBL), C-V characteristics, transconductance, output conductance and RF characteristics of the device have been analyzed at room temperature. The simulation result shows that increase in channel length of H-FGFET results in decreased leakage current, improved switching performance, increased gate capacitance and reduced DIBL. The comparative analysis of H-FGFET with previously reported floating gate FET structures reveal that proposed device offers highest switching ratio. The RF characteristics of H-FGFET illustrates that proposed device can operate efficiently as an amplifier for the frequency range of 0.1 GHz to 100 GHz. Further, the proposed device has also been tested for the detection of nitrogen dioxide gas and results reveal that with increase in operating temperature from 30 °C to 180 °C the leakage current of the device increases from 10−13 to 10−9 and OFF current sensitivity of the proposed sensor changes by 82% on changing the work function of sensing layer from 50 meV to 250 meV.

Normally-off recessed gate β-Ga2O3 MOSHFETs with a modulation-doped heterostructure back-barrier

This study demonstrates enhancement-mode recessed-gate β-Ga2O3 metal–oxide–semiconductor heterojunction field-effect transistors (MOSHFETs) with a combination of the MOS channel and a modulation-doped heterostructure to improve maximum drain current and on-resistance (RON). In this proposed device concept, modulation doping in the heterostructure back-barrier inserted into the MOS channel increases the electron density in the MOS channel while maintaining a normally-off operation. First, 2D simulations of enhancement-mode recessed-gate β-Ga2O3 metal–oxide–semiconductor field-effect transistors (MOSFETs) were performed in a Silvaco ATLAS TCAD environment to calibrate the transfer characteristics with the measured data of the investigated device reported previously. Second, using calibrated physical models and parameters, the transfer and transconductance characteristics, and output and off-state characteristics of the enhancement-mode recessed-gate β-Ga2O3 MOSHFETs were comprehensively investigated. The maximum drain current at VGS = 8 V and VDS = 10 V could be increased up to 32.6 mA mm−1 from 9.1 mA mm−1 with the MOSHFET in comparison with that of the recessed-gate MOSFET. The breakdown voltage increased considerably from 186 V to 226 V for the recessed-gate MOSHFET. The proposed device also showed a lower RON, which decreased from 354 Ω.mm to 214 Ω.mm owing to greater electron accumulation in the channel owing to the introduction of the modulation-doped heterostructure.

Oxide Semiconductor Heterojunction Transistor with Negative Differential Transconductance for Multivalued Logic Circuits.

Multivalued logic (MVL) technology is a promising solution for improving data density and reducing power consumption in comparison to complementary metal-oxide-semiconductor (CMOS) technology. Currently, heterojunction transistors (TRs) with negative differential transconductance (NDT) characteristics, which play an important role in the function of MVL circuits, adopt organic or 2D semiconductors as active layers, but it is still difficult to apply conventional CMOS processes. Herein, we demonstrate an oxide semiconductor (OS) heterojunction TR with NDT characteristics composed of p-type copper(I) oxide (Cu2O) and n-type indium gallium zinc oxide (IGZO) using the conventional CMOS manufacturing processes. The electrical characteristics of the fabricated device exhibit a high Ion/Ioff ratio (∼3 × 103), wide NDT ranges (∼29 V), and high peak-to-valley current ratios (PVCR ≈ 25). The electrical properties of 15 devices were measured, confirming uniform performance in the PVCR, NDT range, and Ion/Ioff ratio. We analyze the device operation by varying the source/drain (S/D) position and changing the device geometry and the thickness of the Cu2O layer. Additionally, we demonstrate heterojunction ambipolar TR to elucidate the transport mechanism of NDT devices at a high gate voltage (VGS). To confirm the feasibility of the MVL circuit, we present a ternary inverter with three clearly expressed logic states that have a long intermediate state and greater margin of error induced by wide NDT regions and high PVCR.

Is there a limit when the access resistance impact on the extraction of key GAA NS FETs devices parameters can (not) be avoided?

DC measurements are performed on n-type Si-channel gate-all-around (GAA) vertically stacked lateral nanosheet (NS) FETs. In this work, the impact of varying external access resistance values on extracted device parameters is analysed. Even if the parameters extraction is made using more access resistance insensitive methodologies, such as Y function-based methods, this work shows that in some cases a higher access resistance can still have an impact on the estimated parameter values, in particular for low field mobility. Moreover, by adding an external resistance only on the source side, the impact of this constructed asymmetry is evidenced on the drain current and transconductance characteristics even at low applied drain bias. The impact of the asymmetry may be enhanced by increasing the applied drain bias. A novel and intuitive Y-function strategy is used to estimate the main device electrical parameters.

A reconfigurable binary/ternary logic conversion-in-memory based on drain-aligned floating-gate heterojunction transistors

A new type of heterojunction non-volatile memory transistor (H-MTR) has been developed, in which the negative transconductance (NTC) characteristics can be controlled systematically by a drain-aligned floating gate. In the H-MTR, a reliable transition between N-shaped transfer curves with distinct NTC and monolithically current-increasing transfer curves without apparent NTC can be accomplished through programming operation. Based on the H-MTR, a binary/ternary reconfigurable logic inverter (R-inverter) has been successfully implemented, which showed an unprecedentedly high static noise margin of 85% for binary logic operation and 59% for ternary logic operation, as well as long-term stability and outstanding cycle endurance. Furthermore, a ternary/binary dynamic logic conversion-in-memory has been demonstrated using a serially-connected R-inverter chain. The ternary/binary dynamic logic conversion-in-memory could generate three different output logic sequences for the same input signal in three logic levels, which is a new logic computing method that has never been presented before.

Verilog-A модель эффекта вымораживания примеси в LDD областях при криогенных температурах

The article shows the practical implementation of the impurity freeze-out effect in the lightly-doped areas of the drain and source (LDD) in the Verilog-A model of the resistor. This model is based on a theoretical understanding of the freeze-out effect at cryogenic temperatures and data from the TCAD simulation of a MOSFET. The TCAD simulation data were represented by transconductance characteristics of n- and p-channel transistors Id(Vg) in linear mode (Vd=0.1 V) at temperature range from -200 °C to 27 °C for transistors with dimensions 10 um × 10 um. The model is applicable to the use as part of a macromodel of a MOSFET transistor for a CMOS bulk process with a supply voltage of 1.8 V and a minimum channel length of 0.18 um. Since the model is based on a limited set of TCAD modeling data, this version is the basis on which it is possible to build a geometrically scalable model that will be valid over the entire range of drain voltages.

Novel approach for implementing ternary value logic devices showing negative differential transconductance characteristics by Fowler–Nordheim tunneling

Ternary value logic (TVL) devices are gaining attention owing to the limitations of binary devices in handling the increasing amount of information. However, the development of ternary devices has been hindered by the complex structures and use of materials lacking CMOS compatibility. This study presents a novel approach to develop ultra-simple TVL devices using thin-tunnel gate dielectrics of AlOx films and TiO2 channel layer. TVL devices are obtained by employing TiO2-based transistors with AlOx films as an oxide tunneling dielectric layer. The device exhibits typical transistor switching characteristics at low gate voltage (VG) and negative differential transconductance owing to Fowler−Nordheim tunneling current at high VG. The reversible implementation of three states, namely, ON, intermediate (INT), and OFF, with the same probability, is demonstrated with excellent reproducibility even after 200 cycles. A circuit is constructed to demonstrate the three output voltage states with respect to the input voltage by connecting the TVL device to a resistor. Additionally, the value and width of the plateau region of the INT output voltage state can be tuned by adjusting the variable resistance values. These highly simplistic TVL devices have the potential for application in low-power, highly integrated, and ultra-miniature electronic devices, thanks to their high level of CMOS compatibility.

Comparative study of Negative Capacitance Field Effect Transistors with different doped hafnium oxides

Negative Capacitance Field Effect Transistors are well known for their superior performance over MOSFET and are a viable candidate to succeed the baseline FET in time ahead. We have studied the performance of 32 nm planar MOSFET with doped hafnium dioxide as a ferroelectric material. The functioning of the NCFET is entirely dependent on the equivalence between the ferroelectric and MOS capacitance. Our simulation results clearly indicated that the Sr doped HfO2 has close capacitance matching with MOS capacitance, when compared with other dopant material (Si, Al and Zr). This also reflects in the performance parameters (drain current and transconductance characteristics) of the device designed. Also, we have designed a resistive load inverter with doped hafnium dioxide, Sr doped among them has an edge over the other ferroelectric material in terms of noise margin and static power dissipation.

Effects of Hydrogen on Endurance Characteristics in NAND Flash Memories

This study comprehensively investigates the effect of hydrogen content in forming gas annealing (FGA) on the endurance of NAND flash memories by statistically analyzing the transconductance () characteristics. The degradation () worsened with higher cycling temperature, delayed time period from erasing to programming () operation, and higher word-line bias () during Moreover, these effects become more pronounced as the hydrogen content in FGA increases. Using the measured distributions and Monte -Carlo TCAD technology, the activation energy () of oxide damage creation can be extracted. The extracted values were 50 meV and 160 meV for the diluted (4%) and pure (100%) hydrogen samples, respectively. This suggests that a higher hydrogen concentration results in more ionized hydrogen atoms remaining in the oxide layer. During these hydrogen ions can drift near the Si/SiO2 surface, where they may react to form trap states. is revealed to have a linear relationship with respect to where the slope is independent of the hydrogen content in FGA.

Noise Effects in the Design of Digital Circuits Based on CNTFET

In this paper initially we present two CNTFET models: the first, already proposed by us and the second the Stanford model, recalling our method to match the output characteristics and transconductance characteristics between these two models. Then we briefly recall a compact noise model, proposed by us, used to simulate the performance of some digital CNTFET circuits, for which we present the DC, transient and noise analysis. In particular we examine a inverter gate and the proposed analysis allows to determine the optimal value of input voltage which makes the noise effects negligible.

Comprehensive modeling of the extrinsic transconductance for InxGa1-xAs/In0.52Al0.48As quantum-well high-electron-mobility transistors

This paper presents the comprehensive modeling of extrinsic transconductance (gm_ext) in the saturation regime for InxGa1-xAs/In0.52Al0.48As quantum-well (QW) high-electron-mobility transistors (HEMTs) with Lg from 10 μm to sub-100 nm, covering the ballistic and mobility relevant regimes. First, we fabricated and characterized two types of lattice matched (LM) channel In0.53Ga0.47As QW HEMTs on a 3-inch InP substrate. One of these was fully fabricated with an i-line stepper, yielding Lg from 10 μm to 0.5 μm, and the other was fabricated in a mix & match manner with a combination of an i-line stepper and an e-beam lithography equipment, where T-shaped gates were implemented using a tri-layer resist stack of ZEP520A-PMGI-ZEP520A in the e-beam lithography process. Using devices with a wide range of Lg values, we examined the transconductance (gm) characteristics in saturation and attempted to correlate them to analytical expressions capable of describing the carrier transport properties of the devices using only physical parameters, such as the gate capacitance (Cgi) apparent mobility (μn_app), and saturation velocity (vsat), and the series resistances (Rs and Rd). In this way, we assessed the dependences of the extrinsic transconductances of the fabricated devices on their gate lengths, with the model parameters of Cgi = 0.65 μF/cm2, μn_app = 9400 cm2/V⋅s, vsat = 4.3 × 107 cm/s and Rs = 147 Ω⋅μm. These values were observed to be well-matched with those of the physical parameters. Most importantly, we extended the proposed approach to realistically project the increase in gm_ext that could be accomplished by improving certain device parameters.

Implementation of Noise Effects on CNTFET-based NOT Gate in Verilog-A

In this paper we initially present two CNTFET models: the first is already proposed by us and the second is the Stanford model, proposing a method to match the output characteristics and transconductance characteristics between these two models. Then we describe a compact noise model, used to simulate the performance of a NOT gate, in order to analyze how the noise sources constitute a significant limitation in the design of circuits based on CNTFET. All simulations are obtained using the programming language Verilog-A on the simulator Advanced Design System (ADS), highlighting the solutions proposed in order to use this software.

β‐(Al0.17Ga0.83)2O3/Ga2O3 Delta‐Doped Heterostructure MODFETs with an Ultrathin Spacer Layer and a Back‐Barrier Layer: A Comprehensive Technology Computer‐Aided Design Analysis

The output characteristics of β‐(Al0.17Ga0.83)2O3/β‐Ga2O3‐based heterostructure modulation‐doped field‐effect transistors (MODFETs) with an ultrathin spacer layer and a back‐barrier layer are fitted with experimental measurements using a Silvaco ATLAS technology computer‐aided design (TCAD) simulation environment, and the calibration of the physical model and material parameters is realized. The effects of spacer layer thickness, barrier layer thickness, Si‐δ doping density, and insertion of a β‐Ga2O3 cap layer on the transfer and transconductance characteristics are examined. It is found that a β‐Ga2O3 cap layer on the top of the heterostructure can increase the sheet carrier density in the heterostructure. A breakdown analysis is also carried out to reveal the effects of several layers on the off‐state characteristics. A range of channel layer thicknesses from 15 to 25 nm is found to be the optimum range to avoid a high off‐state leakage current and earlier breakdown voltage.

Optimization of channel structure and bias condition for signal-to-noise ratio improvement in Si-based FET-type gas sensor with horizontal floating-gate

Sensing performances of the Si-based field-effect transistor (FET)-type gas sensor are not only affected by sensing material characteristics but also by electrical properties of a transducer. Therefore, the optimization of transducer properties, including subthreshold swing, transconductance, and low-frequency noise (LFN) characteristics, is necessary for improving the sensing performances. In this paper, NO2 gas sensing properties, LFN characteristics, and signal-to-noise ratio (SNR) of the FET-type gas sensor having different channel structures (surface and buried channel FETs) are investigated. An n-type indium-gallium-zinc oxide (IGZO) thin-film is used as a sensing layer. The LFN characteristics of both sensors are explained using a carrier number fluctuation model with correlated mobility fluctuation. The flat-band voltage fluctuation (SVfb) value of the buried channel (4.54×10−10 V2/Hz) is smaller than that of the surface channel (2.73×10−9 V2/Hz). Thus, the SNR of the sensor with a buried channel shows ~10 times larger SNR than that with a surface channel. Also, the optimal bias conditions for both sensors are suggested. The sensor with buried channel FET has a limit of detection (LOD) of 44.2 ppt to NO2 gas.

Emergence of multiple negative differential transconductance from a WSe2 double lateral homojunction platform

Recent advances in two-dimensional (2D) van der Waals heterostructures have re-spurred the investigation of non-linear negative differential carrier transport transistors as a potential ingredient for the upcoming digital-driven hyperconnected era. Although notable findings employing various 2D heterojunctions have been recently demonstrated, the performance metrics are insufficient to fulfill requirements for practical device applications, and fundamental difficulties associated with multiple vertical stacking processes in device fabrication must be resolved. Here, we report the realization of multiple negative differential transconductance (NDT) and resistance (NDR) characteristics obtained from a single p-i-n WSe2 double lateral homojunction (DLHJ) transistor. Forming the DLHJ through the selective surface charge transfer doping of a homogeneous bilayer WSe2 film, double NDT characteristics that excel those expected from individual junction components and have high peak-to-valley current ratios (PVCRs) of 36.6 and 12.9 are achieved. Performing combined experimental characterizations and first-principle calculations, obtained exceptional NDT performance at room temperature is determined to originate from the modulation of trap-assisted tunneling and nonlinear 2D band shifts in response to the gate control. Furthermore, the quaternary logic operation based on the triple NDR with the largest PVCR of 137 is achieved by the correlated biasing of the WSe2 DLHJ device.

Homemade-HEMT-based transimpedance amplifier for high-resolution shot-noise measurements.

We report a cryogenic transimpedance amplifier (TA) suitable for cross-correlation current-noise measurements. The TA comprises homemade high-electron-mobility transistors with high transconductance and low noise characteristics, fabricated in an AlGaAs/GaAs heterostructure. The low input-referred noise and wide frequency band of the TA lead to a high resolution in current-noise measurements. The TA's low input impedance suppresses unwanted crosstalk between two distinct currents from a sample, justifying the advantage of the TA for cross-correlation measurements. We demonstrate the high resolution of a TA-based experimental setup by measuring the shot noise generated at a quantum pointcontact in a quantum Hall system.

Pentacene Based Organic Field Effect Transistor Using Different Gate Dielectric

This paper presents the electrical behavior of the top contact/ bottom gate of an organic field-effect transistor (OFET) utilizing Pentacene as a semiconductor layer with two distinctive gate dielectric materials Polyvinylpyrrolidone (PVP) and Zirconium oxide (ZrO2) were chosen. The influence of the monolayer and bilayer gates insulator on OFET performance was investigated. MATLAB software was used to simulate and determine the electrical characteristics of a device. The output and transfer characteristics were studied for ZrO2, PVP and ZrO2/PVP as an organic gate insulator layer. Both characteristics show a high drain current at the gate dielectric ZrO2/PVP equal to -0.0031A and -0.0015A for output and transfer characteristics respectively, this can be attributed to an increase in the dielectric capacitance. Trans conductance characteristics also studied the gate dielectric materials and show the ZrO2/PVP gate dielectric having a higher value from the monolayer, indicating the effect of dielectric capacitance.

Effect of active layer thickness variation on scaling response in a-IGZO thin film transistors under Schottky limited operation

Active layer thickness variation in highly-doped amorphous indium-gallium-zinc oxide thin film transistors with molybdenum-chromium contacts is studied to reveal parametric dependencies under both channel length and gate-contact overlap length scaling. Devices with thickness variations from 5 nm to 30 nm, channel length variation from 3 µm to 100 µm and gate-contact overlap length variation from 1 µm to 10 µm were fabricated, characterized and analyzed. Analysis from a field effect transistor perspective show typical thickness variation trends where threshold voltage shifts positively, subthreshold slope improves and I on/I off ratio increases as the active layer thickness is scaled down. Peculiar observations like extremely low saturation voltage, insensitivity towards channel length variations, two different slopes in the subthreshold region and peaks in the transconductance characteristics can be explained only by invoking the principle of Schottky transistor operation. Thinner devices exhibit high field Schottky operation with barrier lowering which causes monotonously increasing transconductance, while thicker devices show low field behavior with no barrier lowering signified by peaks with saturated behavior of transconductance. Channel length modulates this dependence of transconductance on thickness. Sensitivity towards gate-contact overlap length scaling increases with thickness. Devices with active layer thickness of 5 nm can withstand overlap length scaling up to 5 µm without transconductance degradation, while devices of 10 nm thickness can withstand overlap length scaling only upto 10 µm. Devices of 30 nm thickness show contact limited operation even at 10 µm overlap length. Conventional FET operating principles cannot explain these observations and the phenomenon of Schottky contact transistor operation has been invoked. The results point towards a thin borderline in low dimensional transistors, differentiating a FET from Schottky contact transistors, through a field dependent barrier lowering mechanism, which is modulated by active layer thickness, channel length and gate contact overlap length.