Traditional Phase-locked Loop Research Articles

Impedance remodeling control strategy of grid-connected inverter with inertia-damping phase-locked loop under extremely weak grid

The operation of the grid-connected inverter (GCI) in weak grid conditions presents a risk of instability due to the presence of high grid impedance and the negative impedance effect of the phase-locked loop (PLL). In response to this issue, this paper introduces an impedance remodeling control strategy for the GCI utilizing the inertia-damping phase-locked loop (ID-PLL). Firstly, the proposed ID-PLL exhibits certain inertia and damping properties in comparison to the traditional PLL (T-PLL), resulting in an enhanced phase margin of the GCI system's equivalent output impedance. Consequently, the adaptation range of the grid impedance increases from 12mH (SCR = 3.00) to 24mH (SCR = 1.37). Next, from the perspective of impedance analysis, this study remodels the PLL impedance and inverter control loop impedance, further improving the amplitude and phase margin of the system's output impedance. As a result, the adaptation range of the grid impedance extends to 33mH (SCR = 1.00), and the transition of grid-connected currents becomes smooth and free of overshoot. Finally, the effectiveness of the proposed control strategy is validated through theoretical analysis and experimental verification.

Control Strategy of Three-level Active Neutral Point Clamped Grid Connected Inverters in Unbalanced Power Grid

Traditional phase-locked loops in three-level active neutral point-clamped inverter grid-connected systems for photovoltaic power generation exhibit a deficiency in the decoupling of positive and negative sequences under unbalanced power grid conditions. To address this issue, this study proposes the implementation of the fourth-order generalized integrator into the phase-locked loop to facilitate positive and negative sequence decoupling. Initially, a 3L-ANPC inverter grid connection system is established. However, under unbalanced grid voltage conditions, the PLL effect of the Decoupled Double Synchronous Reference Frame Phase-Locked Loop is found to be suboptimal, leading to considerable fluctuations and distortions in the output frequency signal. To address these complications, we propose an optimized phase-locked loop structure. In this improved design, the PLL first utilizes the FOGI to filter out multiple harmonics in the grid voltage prior to decoupling the positive and negative sequence voltage. This process effectively mitigates the effect on the PLL, thereby enabling rapid and precise tracking of the grid voltage. Simulation analysis is conducted by using Matlab/Simulink to substantiate the effectiveness of the proposed PLL, demonstrating its ability to reliably lock onto the frequency and phase of the fundamental voltage under conditions of unbalanced power grid voltage.

Sensorless Control Based on the Uncertainty and Disturbance Estimator for IPMSMs With Periodic Loads

The research object in this paper is a single rotor compressor based on the interior permanent magnet synchronous motors (IPMSM) with sensorless control, whose load fluctuates periodically with the mechanical angle. The periodically fluctuating loads can cause obvious periodic fluctuations of motor speed. Meanwhile, the traditional phase-locked loop (PLL) can lead to obvious phase shift and amplitude attenuation. Therefore, the controller is designed from two aspects to make the motor run stably at low speed under the periodic load. Firstly, a speed control based on the uncertainty and disturbance estimator (UDE) is proposed to suppress speed fluctuations caused by the periodic load. Secondly, the phase-locked loop based on the resonance control (R-PLL) is proposed to compensate for the periodic angle and speed errors caused by the phase shift coming from the PLL under the periodic load. The experimental results show that the sensorless control based on the R-PLL and UDE can effectively improve the estimated angle accuracy and suppress the speed fluctuations, making the motor run stably at low speed under periodic loads.

Small-signal Stability Analysis and Improvement with Phase-shift Phase-locked Loop Based on Back Electromotive Force Observer for VSC-HVDC in Weak Grids

Voltage source converter based high-voltage direct current (VSC-HVDC) transmission technology has been extensively employed in power systems with a high penetration of renewable energy resources. However, connecting a voltage source converter (VSC) to an AC weak grid may cause the converter system to become unstable. In this paper, a phase-shift phase-locked loop (PS-PLL) is proposed wherein a back electromotive force (BEMF) observer is added to the conventional phase-locked loop (PLL). The BEMF observer is used to observe the voltage of the infinite grid in the stationary <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\alpha\beta$</tex> frame, which avoids the problem of inaccurate observations of the grid voltage in the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$dq$</tex> frame that are caused by the output phase angle errors of the PLL. The VSC using the PS-PLL can operate as if it is facing a strong grid, thus enhancing the stability of the VSC-HVDC system. The proposed PS-PLL only needs to be properly modified on the basis of a traditional PLL, which makes it easy to implement. In addition, because it is difficult to obtain the exact impedance of the grid, the influence of short-circuit ratio (SCR) estimation errors on the performance of the PS-PLL is also studied. The effectiveness of the proposed PS-PLL is verified by the small-signal stability analysis and time-domain simulation.

A system-level method for hardening phase-locked loop to single-event effects

To mitigate the sensitivity of the charge pump in a traditional Phase-Locked Loop(PLL), a single-event-hardened PLL architecture with a proportional and integral path is proposed. The phase margin of the PLL is kept at 58.16° due to the rational design and the output clock frequency ranges from 0.8 to 3.2 GHz. The circuit-level simulation results reveal that the sensitive volume of the hardened PLL decreases by 80% ∼ 95%. The novel radiation-hardened PLL circuit was implemented in a 28 nm CMOS technology and irradiated with heavy ions with a linear energy transfer between 1.9 and 65.6 MeV•cm2 mg−1. The proposed radiation-hardened PLL shows one order of single-event effects hardness level higher than the conventional PLL.

An improved method of phase-locked loop grid-connected inverter based on capacitor voltage full feedforward

Different from the conventional grid voltage feedforward, the capacitive voltage type full feedforward will not amplify high frequency harmonics, and it can eliminate the capacitor current control and simplify the controller design. However, when the grid impedance is relatively large, the phase-locked loop may increase the current harmonics of the grid-connected inverter, leading to system instability. Therefore, this paper establishes the output impedance model of the grid-connected inverter with full feedforward capacitor voltage including phase-locked loop, and then proposes an improved strategy for adding a low-pass filter in the traditional phase-locked loop, and parameterizes it *Design, so as to achieve the purpose of improving the output impedance phase of the inverter. Finally, the simulation verifies that the inverter using the improved phase-locked loop can effectively improve the quality of the grid current and improve the stability of the inverter system in a weak grid.

Research on phase-locked loop technique based on three-dimensional coordinate transformation

The traditional phase-locked loop (PLL) technique widely used in three-phase four-wire system can only obtain one phase angle, and cannot obtain other parameters of unbalanced voltages, such as the amplitude and phase angle of each phase voltage. In order to improve the performance of PLL in unbalanced three-phase four-wire system with disturbance and reduce the order of PLL to improve the stability of the system, a PLL technique based on three-dimensional (3D) coordinate transformation was proposed in this paper. Firstly, the phase detector error of three-phase unbalanced voltage was deduced based on the 3D coordinate transformation. The error can be regarded as the expression form in Hilbert space after linearizing of it. Based on the correspondence between the orthonormal basis in Hilbert space and the unit vectors in Euclidean space, the error can be mapped to Euclidean space, and the detection control law for each voltage parameter can be designed respectively based on the principle of perpendicular decoupling. Then, the voltage parameter detection control law in Euclidean space is mapped back to Hilbert space, so the PLL technique scheme can be obtained which is beneficial to the implementation in the actual system. The control law of each unbalance indices, such as the amplitude and initial phase of each phase voltage, can be decoupled into a first-order or second-order system, so the system structure is simple, and the control parameter design is convenient. The detection of unbalance indices of the three-phase unbalanced voltages with zero-sequence component can be realized with fast and stable characteristics. The simulation and experiments of the proposed PLL technique are carried out finally under several transient conditions of grid voltages, stable within a quarter cycle at the fastest and always stable in 50 ms, so as to validate the rapidness and stability of the proposed PLL technique.

A new speed adaptive estimation method based on an improved flux sliding-mode observer for the sensorless control of PMSM drives

In this paper, an improved speed adaptive flux sliding-mode observer (FSMO) is presented for the sensorless control of surface-mounted permanent magnet synchronous motor (PMSM) drives. First, to suppress the chattering of the traditional FSMO, an algorithm for online adjusting the observer gain is designed. In this algorithm, a transition mode is introduced between the existing reaching and sliding modes, and an error criterion function with speed and current is constructed for the three motion modes. Second, to reduce the rotor speed estimation error, a new speed adaptive estimation method is presented instead of the traditional phase-locked loop (PLL). In this method, the adaptive law for estimating the speed is derived using Lyapunov stability and model reference adaptive theories. Meanwhile, the physical meaning of the speed adaptive law is illustrated. Finally, the proposed FSMO scheme is implemented on a TMS320F28335 digital signal processing (DSP) microcontroller-based surface-mounted PMSM sensorless control experimental bench. Test results demonstrate the excellent dynamic performance, robustness and stability of the proposed FSMO under various operating conditions.

PFD with improved average gain and minimal blind zone combined with lock-in detection for fast settling PLLs

In this paper, two Phase frequency detector (PFD) architectures and a PFD with lock-in detection (PFD-LID) are proposed that are designed using the new techniques for selectively resetting the outputs to achieve improved average gain with a lower blind zone. The two proposed PFDs are designed and fabricated using 180 nm CMOS process. The circuits are tested with the variations in the supply voltage from 1.3 V to 1.8 V, achieving higher average gain and the measured blind zone of 3 ps, which is around five times less than earlier reported works. Also, the proposed selective reset techniques are used to design the PFD-LID. Both the PFDs and PFD-LID are validated using the traditional phase-locked loop (PLL) architecture by achieving minimal settling time of the PLL.

An improved Quasi-Type-1 PLL based on paralleled filtering stage

In three-phase grid synchronization applications, the performance of traditional phase-locked loops will decrease under non-ideal grid voltage conditions. In order to solve the above problem, moving average filters (MAF) has been widely studied and utilized in PLLs in recently published papers with the expense of slower transient speed. This paper proposes a paralleled filtering stage to improve the dynamic performance of PLL. The suggested filter with smaller time delay is based on MAF and delay signal cancellation (DSC) operator, which is integrated in quasi-type-1 structure based PLL (QT1-PLL). Compared with differential MAF-PLL (DMAF-PLL) and QT1-PLL, the proposed filter can obtain a faster transient response without degrading phase estimation accuracy. The experimental results demonstrate that the proposed method can provide satisfactory performance.

Position Sensorless Control System of Permanent Magnet Synchronous Linear Motor Based on Sliding Mode Observer with an Improved Phase-Locked Loop

In this paper, position sensorless control system of permanent magnet synchronous linear motor (PMSLM) based on sliding mode observer (SMO) with an improved phase-locked loop (PLL) is studied. Firstly, according to the mathematical model, a SMO is designed for sensorless control PMSLM drive. Thereafter, an improved PLL is proposed to tackle the imperfection of data overflow existed in the traditional PLL. The designed SMO incorporating with the improved PLL can be effectively suppress the pulsation of the estimated position and hence the chattering of the derived electrical angular velocity. At last, simulated and experimental results are presented to verify the effectiveness and feasibility of the position sensorless control system.

A Sub-Synchronous Oscillation Suppression Strategy for Doubly Fed Wind Power Generation System

During the power transmission of doubly-fed induction generator (DFIG), due to the influence of series compensating capacitance and long-distance transmission, DFIG is prone to sub-synchronous oscillation, which damages the stability of the system. By establishing the mathematical model of DFIG system, the cause of sub-synchronous oscillation and its influence on the control strategy of DFIG system are discussed. In order to solve the problem of performance degradation of traditional phase-locked loop (PLL) under sub-synchronous oscillation, an improved PLL is proposed to replace the traditional PLL. Aiming at the problem that the control of rotor side converter(RSC) and grid side converter(GSC) in doubly-fed wind power generation system under sub-synchronous oscillation is disturbed by harmonic signals, a control method of adding a quasi resonant controller in the control link of RSC and GSC to suppress sub-synchronous oscillation is proposed, and the feasibility of the method is verified by simulation and experiment. Finally, based on the research process of RSC direct resonance control, the sub-synchronous oscillation suppression strategy based on harmonic current extraction is proposed for the frequency adaptability of the quasi resonant controller. The actual performance of the sub-synchronous oscillation suppression strategy is verified through simulation and experiment. The experimental results show that the strategy is effective.

Unconventionally Designed Tracking Loop Adaptable to Plasma Sheath Channel for Hypersonic Vehicles.

An aircraft that moves through the atmosphere at hypersonic speed is covered by plasma sheath, which causes random and fast time-varying amplitude attenuation and phase fluctuation in received signals. This paper comprehensively analyzes the mechanism of the amplitude attenuation effects on a traditional phase-locked loop (PLL), which is always ignored in traditional scenarios (such as satellite telemetry and vehicle communication). Simulation results and theoretical analysis showed that traditional PLL does not work reliably for signal carrier tracking with the severe time-varying amplitude attenuation of the plasma sheath channel. In this paper, an unconventionally designed Kalman filter (KF) tracking loop that is aware of phase dynamics and amplitude attenuation fluctuation for hypersonic vehicles is proposed. To introduce time-varying amplitude attenuation into the proposed KF-based tracking loop, the amplitude attenuation is first modeled with an autoregressive model. The statistical characteristics of the amplitude and phase fluctuation are then incorporated into the state equation and observation equation. Simulation results indicate that the proposed tracking loop is stable when the signal-to-noise ratio is −10 dB with the Ka band, even in the most severe flight environment for hypersonic vehicles.

An Adaptive Feed-Forward Phase Locked Loop for Grid Synchronization of Renewable Energy Systems under Wide Frequency Deviations

Synchronization is a crucial problem in the grid-connected inverter’s control and operation. A phase-locked loop (PLL) is a typical grid synchronization strategy, which ought to have a high resistance to power system uncertainties since its sensitivity influences the generated reference signal. The traditional PLL catches the phase and frequency of the input signal via the feedback loop filter (LF). In general, to enhance the steady-state capability during distorted grid conditions generally, a filter tuned for nominal frequency is used. This PLL corrects large frequency deviations around the nominal frequency, which increases the PLL’s locking time. Therefore, this paper presents an adaptive feed-forward PLL, where the input signal frequency and phase under large frequency deviations are tracked precisely, which overcomes the above-mentioned limitations. The proposed adaptive PLL consists of a feedback loop that reduces the phase error. The feed-forward loop predicts the frequency and phase error, and the frequency adaptive FIR filter reduces the ripples in output, which is due to input distortions. The adaptive mechanism adjusts the gain of the filter in accordance with the supply frequency. This reduces the phase and frequency error and also decreases the locking time under wide frequency deviations. To verify the effectiveness of the proposed adaptive feed-forward PLL, the system was tested under different grid abnormal conditions. Further, the stability analysis has been carried out via a developed prototype test platform in the laboratory. To bring the proposed simulations into real-time implementations and for control strategies, an Altera Cyclone II field-programmable gate array (FPGA) board has been used. The obtained results of the proposed PLL via simulations and hardware are compared with conventional techniques, and it indicates the superiority of the proposed method. The proposed PLL effectively able to tackle the different grid uncertainties, which can be observed from the results presented in the result section.

A Comparative Performance Analysis of GPS L1 C/A, L5 Acquisition and Tracking Stages Under Polar and Equatorial Scintillations

This article provides a comparative performance analysis of different acquisition and tracking methods of GPS L1 C/A and GPS L5 signals testing their robustness to the presence of scintillations in the propagation environment. This article compares the different acquisition methods in terms of probabilities of detection/false alarm, peak-to-noise floor ratios for the acquired signal and execution time, assessing the performance loss in the presence of scintillations. Moreover, robust tracking architectures that are optimized to operate in a harsh ionospheric environment have been employed. The performance of the carrier tracking methods, namely, traditional phase-locked loop (PLL) and Kalman filter based-PLL, have been compared in terms of the standard deviation of Doppler estimation, phase error, phase lock indicator (PLI), and phase jitter. The article is based on real global navigation satellite systems (GNSS) signals affected by significant phase and amplitude scintillation effects, collected at the South African Antarctic research base (SANAE IV) and Brazilian Centro de Radioastronomia e Astrofisica Mackenzie (CRAAM) monitoring stations. Performance is assessed exploiting a fully software GNSS receiver, which implements the different architectures. The comparative analysis allows to choose the best setting of the acquisition and tracking parameters, in order to allow the operation of signal acquisition and tracking at a required performance level under scintillation conditions.

A Dividerless Ring Oscillator PLL With 250fs Integrated Jitter Using Sampled Lowpass Filter

This brief presents a novel ring oscillator based phase lock loop architecture that is capable of wideband, dividerless integer-N synthesis. The noise transfer function of the presented architecture is the same as a sub-sampling phase lock loop (PLL). Like a sub-sampling PLL, the presented architecture removes the phase detector and charge pump’s $N^{2}$ noise that dominates the in-band noise of traditional PLLs. This noise reduction allows the presented ring oscillator PLL to operate with integrated jitter as low as 250fs. Unlike sub-sampling PLLs, the presented architecture moves the sampling block downstream of the loop filter. As the sampled data is lowpass filtered, only low frequency sampling blocks are required, which removes the power and area overheads associated with directly sampling the voltage controlled oscillator. Measurement results show the presented PLL is capable of locking over a wide range of 1.2-2.5GHz. The presented PLL is fabricated in 65nm bulk CMOS, and demonstrates a figure of merit of −242.7dB, which is among best in class for ring oscillator PLLs. Furthermore, an area of 0.0066 mm2 is consumed, which represents the smallest published sub-sampling ring oscillator PLLs.

Phase-Locked Strategy of Photovoltaic Connected to Distribution Network With High Proportion Electric Arc Furnace

With the rapid development of industrialization, the proportion of electric arc furnaces (EAF) in distribution networks is getting higher and higher. Aiming at the problem that grid voltage is distorted by a large number of arc furnace nonlinear loads accessing to distribution networks, it is crucial to make dynamic analysis of distribution network voltage and adopt a control strategy of grid-connected converter based on the new phase-locked loop (PLL) technology. As a result, the harmonic distortion rate is reduced and the quality of grid-connected current and voltage is improved. In this paper, photovoltaic (PV) system model and the typical dynamic model of the EAF are established. By analyzing the influence of the EAF model on the PV grid-connected converter with the traditional phase-locked loop while connected to distribution network, a control strategy of the PV grid-connected converter with the self-adjusting double SOGI (MAF-SASOGI) phase-locked loop with the ideal low-pass filter is proposed. Through the simulation analysis, it is verified that precise phase locked can be realized and harmonic content of the system can be reduced by the PLL strategy proposed in this paper. Therefore, the quality of PV grid-connected voltage and current is improved.

A 1–2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation

This paper proposes computational locking (C-lock) in all-digital phase-locked loops (PLLs) to achieve rapid frequency and phase lock acquisition. The proposed approach employs a “lock-accelerator” module that accelerates lock-times ( $T_{\mathrm{ lock}}$ ) in both cold-start (PLL power-up) and re-lock scenarios without impacting steady-state PLL performance. The key premise underlying C-lock is that solving a system of accurate phase-frequency update equations at run-time provides superior lock performance compared to traditional PLLs that rely on linear feedback control. C-lock is readily amenable to runtime adaptation to Process, Voltage, and Temperature (PVT) variation. A 1–2 GHz computationally locked PLL was implemented in a 65-nm standard CMOS process. Measurements over 50 000 iterations of re-lock and cold-start experiments across multiple test-chips, supply-voltage ( $V_{\mathrm{ dd}}$ ), and operating temperatures indicate a mean re-lock time of 12 PLL reference clock cycles (12 $T_{\mathrm{ REFCLK}}$ ), and a “cold-start” $T_{\mathrm{ lock}}$ of 16 $T_{\mathrm{ REFCLK}}$ . Although the silicon demonstration of C-lock is based on a PLL designed for system clocking applications, the proposed approach is applicable to a broader class of PLLs.

Reactive Power Compensation in Distribution Systems Through the DSTATCOM Integration Based on the Bond Graph Domain

In this paper, the distribution static compensator model based on the bond graph (BG) domain is presented. The methodology is applied to reactive power compensation in distribution systems where a traditional phase lock loop for sensing the AC grid frequency is not needed. The control law is developed using the inverse BG model, which is extracted using the bi-causality concept. In this way, it is possible to perform the distribution system analysis completely in the BG domain. This means that the graphical model is inverted by obtaining the open-loop control law structure, and then the close loop is formulated. The balanced and unbalance conditions are analyzed, generating a control structure that is robust and efficient. The efficacy of the proposed methodology is shown through: partial and complete system simulations in MATLAB/Simulink® (MATLAB r2015b, Natick, Massachusetts, 01760, USA), as well as experimental laboratory tests. Such tests use: the rapid control prototyping concept and the real-time simulator Opal-RT Technologies® (Montreal, QC, Canada).

PERFORMANCE OF GNSS CARRIER-TRACKING LOOP BASED ON KALMAN FILTER IN A CHALLENGING ENVIRONMENT

Abstract. The global navigation satellite system (GNSS) recently plays an extremely important role in positioning, navigation, and timing (PNT) applications for the modernized automations and mechanizations, e.g., unmanned aerial vehicles (UAVs), unmanned ground vehicles (UGVs), military aircrafts, etc. Nevertheless, GNSS signals are very vulnerable to the influence of various interferences when they are received on Earth, and the reason why it happens is that the long line-of-sight (LOS) distance between the satellite and the receiver user dramatically reduces the power strength after the signal reaches at the ground. The weak GNSS signal is hard to be handled with traditional phase lock loop (PLL), especially in a dynamic environment. Again, the trade-off among the coherent integration time of tracking loop, received signal power strength, and signal or user receiver dynamics is still a tough and remained problem to be solved. The Kalman filter (KF) is always a promising tool to efficiently decrease the random noise for the tracking process. In our work, we evaluate the performances of the tracking loop modelled with both standard KF and extended Kalman filter (EKF). An adaptive algorithm for the covariance matrix of the process noise is contained in our system to increase the tracking ability in a weak and dynamic environment. Besides, a noise channel is also contained to automatically adjust the priori measurement covariance for the KF tracking loop model. Simulation results demonstrate the performance with the proposed technique.