Traditional ATPG Research Articles

Improving Quality of Manufacturing Test using Cell-Aware ATPG

The existing fault models like stuck-at, small delay defect, transition, and bridge fault models and their associated patterns are becoming less efficient, as the technology moves to increasingly smaller geometries. It is because traditional defect models target the faults only on IC gate boundaries, and the interconnects between the cells, but a significant population of defects (perhaps up to 50%) occurs within the cells or gates which are not specifically targeted by existing ATPG fault models. In this paper, a new ATPG methodology known as the Cell-aware test is implemented explicitly to target the defects caused by cell-internal open and short faults and improve the manufacturing test quality by minimizing the test escapes. This work explains how a Cell-Aware ATPG method performs a characterization on the GDSII data of library cell`s to produce a CAT library view (UDFM), test Pattern generation, and comparison between Traditional and Cell-Aware ATPG. The Cell-Aware ATPG is implemented using Tessent Testkompress, traditional ATPG is also developed to study and analyze both ATPG methodologies comparatively. Experiment results show a significant improvement in faults being targeted at an expense of an increase in pattern count and run-time. Obtained 71.28% and 59.38% test coverage for UDFM static and UDFM delay respectively. Achieved significant improvement in the test escapes with Cell-Aware Patterns when compared to traditional ATPG patterns.

On Design Validation Using Verification Technology

Despite great advances in the area of Formal Verification during the last ten years, simulation is currently the primary means for performing design verification. The definition of an accurate and pragmatic measure for the coverage achieved by a suite of simulation vectors and the related problem of coverage directed automatic test generation are of great importance. In this paper we introduce a new set of metrics, called the Event Sequence Coverage Metrics (ESCMs). Our approach is based on a simple and automatic method to extract the control flow of a circuit so that the resulting state space can be explored for validation coverage analysis and automatic test generation. During simulation we monitor, in addition to state and transition coverage, whether certain control event sequences take place or not. We then combine formal verification techniques, using BDDs as the underlying representation, with traditional ATPG and behavioral test generation techniques to automatically generate additional sequences which traverse uncovered parts of the control state graph, or exercise an uninstantiated control event sequence.

Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays

Test and validation of embedded array blocks remains a major challenge in today‘s microprocessor design environment. The difficulty comes from twofold, the sizes of the arrays and the complexity of their timing and control. This paper describes a novel test generation methodology for test and validation of microprocessor embedded arrays. Unlike traditional ATPG methods, our test generation method is based upon the high-level assertion specification which is originally used for the purpose of formal verification. The superiority of these assertion tests over the traditional ATPG tests will be discussed and shown through various experiments on recent PowerPC microprocessor designs.

Abstraction techniques for validation coverage analysis and test generation

The enormous state spaces which must be searched when verifying the correctness of, or generating tests for, complex circuits precludes the use of traditional approaches. Hard-to-find abstractions are often required to simplify the circuits and make the problems tractable. This paper presents a simple and automatic method to extract the control flow of a circuit so that the resulting state space can be explored for validation coverage analysis and automatic test generation. This control flow, capturing the essential "behavior" of the circuit, is represented as a finite state machine called the ECFM (Extracted Control Flow Machine). Simulation is currently the primary means of verifying large circuits, but the definition of a coverage measure for simulation vectors is an open problem. We define functional coverage as the amount of control behavior covered by the test suite. We then combine formal verification techniques, using BDDs as the underlying representation, with traditional ATPG techniques to automatically generate additional sequences which traverse uncovered parts of the control state graph. We also demonstrate how the same abstraction techniques can complement ATPG techniques when attacking hard-to-detect faults in the control part of the design for which conventional ATPG alone proves to be inadequate or inefficient at best. Results on large designs show significant improvement over conventional algorithms.