Total Test Application Time Research Articles

Software-Based Self-Testing of Symmetric Shared-Memory Multiprocessors

Software-based or instruction-based self-testing has recently emerged as an effective alternative for the manufacturing and online testing of microprocessors, and is progressively adopted by major microprocessor manufacturers mainly as a supplement to other mature and well-established testing approaches to reach higher test quality. Thus far, software-based self-test approaches presented in the literature have focused almost exclusively on uniprocessors. With the continuing prevalence of multiprocessors, the focus of such research approaches moves from the uniprocessor to the multiprocessor case. In this paper, we study the application of software-based self-testing on symmetric shared-memory multiprocessors (SMP) considering the most common interconnection architectures, shared bus and crossbar switch. We focus on the impact of the shared-memory system architecture, the cache coherence mechanisms, and the interconnection architecture on the execution time of self-test programs running on each separate core and exploit the SMP's parallelism during testing to reduce the test execution time. We propose a generic methodology that allocates the test programs and test responses into the shared on-chip memory and schedules the test routines among the cores aiming at the reduction of the total test application time, and thus, test cost, for the SMP, by increasing the execution parallelism and reducing both bus contentions and data cache invalidations. We demonstrate the proposed solutions with detailed experiments on several two-core, four-core, and eight-core SMP benchmarks based on a popular RISC benchmark processor using both the shared bus and the crossbar switch interconnection architectures.

Test scheduling for core-based systems using mixed-integer linear programming

We present optimal solutions to the test scheduling problem for core-based systems. Given a set of tasks (test sets for the cores), a set of test resources (e.g., test buses, BIST hardware) and a test access architecture, we determine start times for the tasks such that the total test application time is minimized. We show that the test scheduling decision problem is equivalent to the m-processor open shop scheduling problem and is therefore NP-complete. However a commonly encountered instance of this problem (m=2) can be solved in polynomial time. For the general case (m>2), we present a mixed-integer linear programming (MILP) model for optimal scheduling and apply it to a representative core-based system using an MILP solver available in the public domain. We also extend the MILP model to allow optimal test set selection from a set of alternatives. Finally, we present an efficient heuristic algorithm for handling larger systems for which the MILP model may be infeasible.

Gradually-on structure for scan design

A new structure named the gradually-on (GO) structure for the full/partial scan design of sequential circuits is proposed. Because this structure allows the scan cells to be turned on gradually, the total test application time can be dramatically reduced.