Total Harmonic Distortion Calculation Research Articles

Numerical Simulation of the Carbon Deposition Mechanism of Solid Oxide Fuel Cells Based on Total Harmonic Distortion Analysis

Identifying the corresponding degradation mechanisms at the early stage of operation is important for the long-term stable operation of solid oxide fuel cells (SOFCs). This paper uses total harmonic distortion analysis (THDA) to identify the anode carbon deposition mechanism in the early stage of SOFC operation with carbon-containing fuels. An accelerated calculation model for the electrochemical impedance spectrum (EIS) and a total harmonic distortion calculation model were constructed to study the carbon deposition mechanism and carbon removal strategy of SOFC anodes based on a one-dimensional transient elementary reaction kinetic model of an SOFC fueled by a CH4/H2O mixture. It is shown that the THDA calculation model can identify the primary stages of carbon deposition on SOFC anodes at specific frequencies. The THDA profiles at frequencies greater than 2 kHz contain essentially the same key information as at lower frequencies, suggesting that THDA can significantly reduce the test time for identifying performance degradation in the early stages of SOFC operation compared to EIS. Using a mixture of hydrogen and water vapor to remove the solid carbon generated by the cell anode and restore it to its initial performance, the THDA computational model can successfully respond to this process.

Application of ANFIS to Minimize Total Harmonic Distortion in Brushless DC Motor

Abstract: Total harmonic distortion provides direct impact on power quality in distributed systems. The work presents reduction of Total harmonic distortion (THD) in Brushless DC motor (BLDC) using adaptiveneuro controller. The configured controller is provided with a rule base, input and output membership functions. The BLDC motor is modelled in MATLAB-SIMULINK with load variation that have direct impact on the functioning of a system. The parameters include load, resistance and inertia of BLDC motor. The work results are obtained after simulating BLDC system under different load configurations. The conclusion is provided with the calculation of THD so produced using Adaptive neuro configured controller

Hybrid control mechanism-based DVR for mitigation of voltage sag and swell in solar PV-based IEEE 33 bus system

<p><span lang="EN-US">The power quality issues are raised due to sag/swell, which affects the overall performance of the grid-connected system. This study introduces the hybrid control mechanism based on a dynamic voltage restorer (DVR) to mitigate the sag and swell issues in the solar PV-based IEEE 33 bus system. The hybrid controller improves the dynamic performance and boosts the overall efficiency of the DVR system. The proposed work is also used to address the distribution system's voltage quality issues with minimal energy drawn out from the utility grid and effectively use solar energy. The sag and swell are introduced at the grid side and compensated at the load side by injecting DVR voltage. The proportional-integral (PI) controller followed by the fuzzy logic controller (FLC) is used to create the hybrid control mechanism for DVR. In this work, the solar PV system with DVR system is connected to the 29<sup>th </sup>location in the IEEE 33 bus system for performance realization. The hybrid control mechanism-based DVR provides 1.06% and 1.05% total harmonic distortion (THD) at sag and swell conditions for load voltage. The proposed work meets the IEEE 519 standards in terms of THD calculation. The proposed design compares with existing work and shows better THD reduction for load voltages.</span></p>

Sensorless Voltage Estimation for Total Harmonic Distortion Calculation Using Artificial Neural Networks in Microgrids

In this brief, a sensorless voltage estimation approach for total harmonic distortion (THD) calculation is proposed to reduce number of voltage sensors in the microgrids. The intelligent proposed method provides a cost-effective and reliable voltage estimation and THD calculation of the desired bus in the multi-bus microgrid based on the artificial neural networks (ANNs). In the proposed method, the output voltage and current of distributed generation units along with the voltage of the desired bus are used to train the ANN offline. The trained ANN is then used to estimate the voltage and calculate both harmonic components, and THD online at the desired bus. The Simulation results show that the proposed approach can effectively estimate the voltage and calculate THD of buses in the multi-bus islanded microgrids.

Realisation of some current-mode fractional-order VCOs/SRCOs using multiplication mode current conveyors

In this paper for the first time a catalogue of linear voltage-controlled fractional-order oscillators employing multiplication-mode current conveyor (MMCC) have been systematically derived using state variable approach. The work also includes detailed relevant analysis of the derived oscillators. Furthermore, three special cases are considered for each of the derived oscillators. Non-ideal analysis has been done for all the oscillators to show the impact of port non-idealities on the frequency. Port parasitics are also examined to justify the deviation between the theoretical and the simulated frequency values against the controlling voltage. Fourier analysis has been carried out to find out the total harmonic distortion figures. Functionality of all the oscillators have been verified on PSPICE utilizing the library files of AD844 and AD835 to realize MMCC. Simulation results are also provided for each special case including the integer-order case. Relevant MATLAB plots are provided for one of the oscillators to facilitate comparison between factional-order and oscillation parameters of the oscillator.

Three‐phase buck–boost PFC rectifier with common‐mode free output voltage and low semiconductor blocking voltage stress

Three-phase buck–boost power-factor correction (PFC) rectifiers are characterised by a unity power-factor mains behaviour and/or sinusoidal input currents and are providing a wide-output voltage range. In this study, an extension of a state-of-the-art three-phase buck–boost PFC rectifier topology is proposed. The DC output of the new topology does not suffer from a high-frequency common-mode voltage with respect to the (grounded) mains star point, which alleviates electromagnetic interference concerns. Also, the blocking voltage requirements of the AC-side switches are reduced significantly (almost by a factor of two for a 400 V line-to-line mains and a 400 V DC output), which facilitates a broad selection of cost-effective power semiconductors for the system's realisation. The rectifier can be controlled with a simple feedback system and the concept is especially suitable for low-power applications. A 1 kW hardware demonstrator is employed to verify the results of theoretical considerations. The system seamlessly operates in the buck and boost regime and achieves conversion efficiencies of 95.3% and mains current total harmonic distortion figures in the range of 1–5%.

Design and Implementation of New Multilevel Inverter Topology for Trinary Sequence Using Unipolar Pulsewidth Modulation

This paper proposes a new multilevel inverter (MLI) topology that utilizes trinary sequence for the dc sources. It gives maximum output voltage level with minimum dc source and switch count when compared to other sequences, such as symmetric, natural, binary, and quasi-linear. This is due to the fact that the trinary sequence generates of all additive and subtractive combinations of input dc levels in the output voltage waveform. The concept is implemented on a 9-level asymmetric MLI using only four active devices. Multicarrier unipolar pulsewidth modulation technique is adopted to create the switching pulses. Theoretical calculation of total harmonic distortion in both voltage and current waveforms has been performed using asymptotic time domain formula. These values are compared with simulation and experimental values for different modulation indices. Power loss calculation for proposed topology is discussed with appropriate mathematical equations.

Class of high step‐up switched Z‐source inverters: steady state analysis and objective function

In this study, high step-up switched Z-source inverters (HSZSIs) with two main groups namely types I and II are proposed. Each of these groups includes several proposed structures. Owing to the features of the proposed structures such as high boost factor ( β ) , continuous input current, and low voltage stress; they can be used in different applications such as renewable power systems. By using the same numbers of the passive elements in comparison with a conventional Z-source inverter (ZSI), quasi-ZSI, and series ZSI (SZSI), the proposed structures produce a higher boost factor. A new objective function is defined so that all compared parameters can be investigated with each other simultaneously. The power losses and efficiency analyses for all of the proposed structures are done and compared with the conventional structures. It is shown that for P out ≃ 200 W , the measured efficiencies for basic HSZSI type I, quasi-HSZSI type I, basic HSZSI type II and quasi-HSZSI type II are 91, 85, 96, and 92%, respectively. In addition, the total harmonic distortion calculation, dynamic performance and designing a closed-loop control method for the proposed structures are shown. Finally, the experimental results are indicated for a 500 W prototype.

Total Harmonic Distortion Comparison between Sinusoidal PWM Inverter and Multilevel Inverter in Solar Panel

This research compared the performance of PWM (Pulse Width Modulation) inverter and multilevel inverter in terms of their output voltage and current total harmonic distortion (THD). The inverters were designed to have the output voltage of 220 V at 50 Hz. The input voltage for both inverters are 400 VDC. For PWM inverter, the PWM technique utilized was sinusoidal PWM (SPWM) and for multilevel converter, the number of voltage level is five with diode-clamped topology. The study included circuit implementation, analysis, and THD calculation, all of which were carried out through simulation using PSpice software. In controlling the SPWM inverter output, the adjusted parameters included amplitude modulation ratio, frequency modulation ratio, and filter components’ parameters. On the other hand, the firing angles of the switching components were designated as controlling parameters in multilevel inverter. From the study, it was found that the best THD values of the designed SPWM inverter are 4.2% (voltage) and 1.7% (current), while those of multilevel inverter are 27% and 11%, for voltage and current, respectively. Thus, it can be concluded that SPWM inverter is better than 5-level inverter for the application in solar panel due to its lower THD. In our study, 5-level inverter did not satisfy the THD requirement specified in IEEE 512-1992, i.e. 5%.

Total Harmonic Distortion at Fault in RLC Load

<p>This paper focuses on the calculation of total harmonic distortion (THD) at various fault situations in case of RLC load. The faults are created by introducing heavy impedance of 1000 ohm, by blowing off the gate pulse at one of the terminals of the mosfet, and by introducing a line to ground fault. The Matlab based simulation has been done to show these effects.</p>

Harmonic Elimination in Multilevel Inverters Under Unbalanced Voltages and Switching Deviation Using a New Stochastic Strategy

A new approach for minimization of total harmonic distortion (THD) of a multilevel flying capacitor inverter (MFCI) based on the selective harmonic elimination named stochastic THD (STHD) strategy is proposed. In the STHD strategy, the step voltage levels of multilevel inverter are considered to be varying due to unbalanced capacitor voltages. Moreover, this paper improves modeling of harmonic elimination by considering the effects of dissipative snubbers, blanking time, gate-drive circuits, and computation time in microcontrollers on the THD calculation. Switching instants are deviated from the desired moments by regarding the mentioned effects. In the proposed strategy, the switching angle variations and unbalancing of flying capacitor voltages are evaluated by $2\,m + 1$ point estimate strategy. Then, the formulation is combined with new modified cuckoo search algorithm and a self-adaptive mutation tactic for the establishment of new robust algorithm for minimization of the THD. The proposed STHD strategy is capable of determining the best switching angles pattern in low switching frequency without measuring current and capacitor voltages, as well as not using any controller. The proposed strategy is applied on three MFCIs and the results show that the proposed method effectively minimizes specific harmonics with low THD.

Optimisation of LCL filter based on closed‐loop total harmonic distortion calculation model of the grid‐connected inverter

A novel optimisation method of LCL filter based on closed-loop total harmonic distortion (THD) calculation model of the grid-connected inverter is proposed in this study. If the parameters of the LCL filter are large enough, the current harmonics can be significantly inhibited. However, the size, weight and price of the filter may increase. If the parameters of the LCL filter are too small, the attenuation of the current harmonics may be not enough. In the proposed method, the target of optimisation is to obtain the minimum value of the inductors on the premise of the allowed current harmonics. The harmonics should be analysed and the control-loop should be taken into consideration. According to this, a closed-loop THD calculation model is established. Generalised reduced gradient (GRG) method is applied to do the optimisation based on the model. With the optimised parameters of LCL filter, the size, weight and price of the filter can be reduced. The relationship between THD and the parameters of the LCL filter is analysed. The principle of GRG is discussed. Finally an 18 kVA three-phase grid-connected inverter with the optimised LCL filter has been established and tested. Simulation and experimental results verify the theoretical analysis.

GA BASED SELECTIVE HARMONIC MINIMIZATION OF A 11 LEVEL CASCADED INVERTER USING PV PANELS

A method for eliminating the lower order harmonics in a 11 level cascaded inverter is presented in this paper. The input for the multilevel inverter is taken from solar panels so that the input voltage will be varying with respect to time. Genetic algorithm is a selective harmonic minimization technique where the switching angles are calculated real time for a set of DC inputs from solar panels. These values of switching angles are applied to a 11 level cascaded H-bridge inverter. This paper will give details regarding the method along with the simulation results and calculation of Total Harmonic Distortion(THD). The target harmonics considered for minimization were 5 th ,7 th ,11 th and 13 th harmonics.

Modified Approach for Harmonic Reduction in Transmission System Using 48-pulse UPFC Employing Series Zig-Zag Primary and Y-Y Secondary Transformer

In this paper THD (Total Harmonic Distortion) is analysed and compared by using UPFC in a multi-line transmission system of 500 KV having 5- buses in two different arrangements. The UPFC converters are arranged as a Diode Clamped multilevel Converter (DCMLC) that leads to the cost reduction as compared with other multi-level converters. The comparison has been done by both series zig-zag/2Y- 2Δ and series zig-zag/4Y transformer configuration for 48-pulses GTO based diode clamped converter. The THD is reduced to 42.59% and 58.82% of input waveform at bus B2 by using series zig-zag/4Y transformer configuration. This transformer converter configuration also reduces the difficulty of designing the transformer winding ratio. For calculation of THD, FFT analysis is carried out using MATLAB.

A Hybrid Multilevel Inverter System Based on Dodecagonal Space Vectors for Medium Voltage IM Drives

Dodecagonal (12-sided) space vector pulsewidth modulation (PWM) schemes are characterized by the complete absence of (6n ± 1)th-order harmonics (for odd n) in the phase voltages, within the linear modulation range and beyond, including overmodulation. This paper presents a new topology suitable for the realization of such multilevel inverter schemes for induction motor (IM) drives, by cascading two-level inverters with flying-capacitor-inverter fed floating H-bridge cells. Now, any standard IM may be used to get the dodecagonal operation which hitherto was possible only with open-end winding IM. To minimize the current total harmonic distortion (THD), a strategy for synchronous PWM is also proposed. It is shown that the proposed method is capable of obtaining better THD figures, compared to conventional dodecagonal schemes. The topology and the PWM strategy are validated through analysis and subsequently verified experimentally.

A Low-Cost Power-Quality Meter With Series Arc-Fault Detection Capability for Smart Grid

This paper presents a low-cost digital single-phase power-quality measurement device for consumer use with a wide range of features, including series arc-fault detection, load trip on failure, and phase/neutral line wiring mix up indication. A wavelet multiresolution analysis technique was utilized for the voltage transient event detection and the current drop pattern recognition, specifically to arc fault. The last feature also involved the use of adaptive thresholding, peak detection, and repetition frequency calculation. A computationally efficient and accurate Goertzel filter was used for total harmonic distortion calculation. In addition, this meter can measure phase fundamental frequency (using the zero-crossing technique), rms values, and power. MATLAB and MathCAD packages were used to build and simulate arc-fault model and phase voltage distortion, to design and test part of the developed algorithms, which were further implemented in Embedded C and Assembler programming languages. A prototype circuit board with the required sensors and relay, analog isolation, indication, user controls, communication link, and a low-cost microchip microcontroller (MCU) dsPIC33 was designed and built to validate implemented algorithms and conduct experiments.

Calculating the Formula of Line-Voltage THD in Multilevel Inverter With Unequal DC Sources

Multilevel inverters introduce harmonics to the network besides their remarkable advantages. Total harmonic distortion (THD) is one of the most important indexes to evaluate the harmonic contents of waveforms. The conventional method of line-voltage THD calculation gives approximate answers, because high-order harmonics are ignored. In this paper, an analytical algebraic method based on formulating the line-voltage THD of multilevel inverters with unequal dc sources is presented. This method, which is general and applicable to each number of switching angles, is implemented to a five-level inverter with staircase waveform as a case study. The implementing process of this method can be easily repeated for each number of levels. The accuracy of the proposed method is illustrated in comparison with the approximate method. Some advantages of the extracted formulas of line-voltage THD are simplicity and rapidity in calculations, considering all harmonics and the possibility of finding optimal switching angles analytically. Experimental results are presented to validate the theory.

A New Structure of Multilevel Inverter with Reduced Number of Switches for Electric Vehicle Applications

Both Hybrid Electric Vehicles (HEVs) and Electric Vehicles (EVs) need a traction motor and a power in-verter to drive the traction motor. The requirements for the power inverter include high peak power, opti-mum consumption of energy, low output harmonics and inexpensive circuit. In this paper, a new structure of multilevel inverter with reduced number of switches is proposed for electric vehicle applications. It consists of an H-bridge and an inverter in each phase which produces multilevel voltage by switching the dc voltage sources in series. As the number of switches are reduced, both conduction and switching losses will be de-creased, which leads to increase the efficiency of converter. The size and power consumption of driving cir-cuits are also reduced. The proposed three phase inverter can produces more number of voltage levels in the same number of the voltage source and reduced number of switches compared to the conventional inverters. This structure minimizes the total harmonic distortion (THD) of the output voltage waveforms. The structure of proposed multilevel inverter, modulation method, switching losses, THD calculation and simulation re-sults with PSCAD/EMTDC software are shown in this paper.

Measuring harmonic distortion in electrical power networks – New approach

Standard specification for power network quality diagnostic systems requires synchronization of sampling rate to the network frequency in every 10 s in order to ensure high accuracy of harmonic analysis. The total harmonic distortion (THD) cumulates measurement errors, therefore it is the most sensitive parameter to the frequency synchronization. This paper investigates two main effects putting impact on the THD computation accuracy. The first is the effect of the base clock rate of sampling hardware and the second is the practical deviation of network frequency during the 10 s synchronization period. The relative accuracy of THD calculation is examined in different real practical solutions and different synchronization methods are discussed and assessed. Theoretical proof and practical demonstration are given to show the needs of special synchronization methods in certain measuring circumstances.

Carrier Distortion in Hysteretic Self-Oscillating Class-D Audio Power Amplifiers: Analysis and Optimization

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> An important distortion mechanism in hysteretic self-oscillating (SO) class-D (switch mode) power amplifiers-–carrier distortion-–is analyzed and an optimization method is proposed. This mechanism is an issue in any power amplifier application where a high degree of proportionality between input and output is required, such as in audio power amplifiers or xDSL drivers. From an average-mode point of view, carrier distortion is shown to be caused by nonlinear variation of the hysteretic comparator input average voltage with the output average voltage. This easily causes total harmonic distortion figures in excess of 0.1–0.2%, inadequate for high-quality audio applications. Carrier distortion is shown to be minimized when the feedback system is designed to provide a triangular carrier (sliding) signal at the input of a hysteretic comparator. The proposed optimization method is experimentally proven in an audio power amplifier leading to THD figures that are comparable to the state of the art. Experimental hardware is a hysteretic SO bandpass current-mode-controlled single-ended audio power amplifier capable of 45 W into <formula formulatype="inline"><tex Notation="TeX">$\hbox{8}\;\Omega$</tex></formula> or 80 W into <formula formulatype="inline"><tex Notation="TeX"> $\hbox{4}\;\Omega$</tex></formula> from a <formula formulatype="inline"><tex Notation="TeX">$\pm\hbox{34}$</tex></formula> V supply with less than 0.03% THD from 100 Hz to 6.7 kHz. Carrier distortion is shown to account for this limitation in THD performance. </para>