Topological Walk Research Articles

Reliability Analysis of Logic Circuits

Reliability of logic circuits is emerging as an important concern in scaled electronic technologies. Reliability analysis of logic circuits is computationally complex because of the exponential number of inputs, combinations, and correlations in gate failures. This paper presents three accurate and scalable algorithms for reliability analysis of logic circuits. The first algorithm, called observability-based reliability analysis, provides a closed-form expression for reliability and is accurate when single gate failures are dominant in a logic circuit. The second algorithm, called single-pass reliability analysis, computes reliability in a single topological walk through the logic circuit. It computes the exact reliability for circuits without reconvergent fan-out, even in the presence of multiple gate failures. The algorithm can also handle circuits with reconvergent fan-out with high accuracy using correlation coefficients as described in this paper. The third algorithm, called maximum- k gate failure reliability analysis, allows a constraint on the maximum number (k) of gates that can fail simultaneously in a logic circuit. Simulation results for several benchmark circuits demonstrate the accuracy, performance, and potential applications of the proposed algorithms.

TOPOLOGICAL PEELING AND APPLICATIONS

We present a new approach, called topological peeling, for traversing a portion AR of the arrangement formed by n lines within a convex region R on the plane. Topological peeling visits the cells of AR in a fashion of propagating a "wave" of a special shape (called a double-wriggle curve) starting at a single source point. This special traversal fashion enables us to solve several problems (e.g., computing shortest paths) on planar arrangements to which previously best known arrangement traversal techniques such as topological sweep and topological walk may not be directly applicable. Our topological peeling algorithm takes O(K + n log (n + r)) time and O(n + r) space, where K is the number of cells in AR and r is the number of boundary vertices of R. Comparing with topological walk, topological peeling uses a simpler and more efficient way to sweep different types of lines, and relies heavily on exploring small local structures, rather than a much larger global structure. Experiments show that, on average, topological peeling outperforms topological walk by 10–25% in execution time.

WALKING IN AN ARRANGEMENT TOPOLOGICALLY

We present topological walk, an on-line algorithm for computing a walk in an arrangement. Here, a walk is a visit to the cells of an arrangement in an order such that consecutive cells are adjacent to each other. The algorithm can walk in a part of an arrangement efficiently; more precisely, given an arrangement of n lines in a convex region containing K cells, a walk is performed in O(K + n log n) time and O(n) working space. Several optimal-cell-finding problems can be solved efficiently applying the topological walk. Further, a construction of a spanning tree with maximum node degree three of the dual graph of an arrangement is given.