Recently, memristive devices (e.g. CBRAM and ReRAM etc.) have been proposed as an alternative to C-MOSFET based neuromorphic device (i.e. neuron and synapse) to achieve a high neuronal density and low power consumption. Among memristive devices, the conductive bridge neuron has been a great attention due to its area efficiency, low power consumption (< 500 fJ), and good C-MOS compatibility 1-3 . However, past researches have mainly focused on stochastic nature of conductive-bridge neurons. In particular, most of the stochastic conductive-bridge neuron have used capacitors to implement membrane potential, which requires a large integration area (~1000F2). In this works, integrate property of Al2O3-based cap-less conductive-bridge neuron was demonstrated which allows a cost-efficient neuromorphic chip by using a same process technology as a memristor synapse, as shown in Fig 1 (a). Note that the Al2O3-based cap-less conductive-bridge neuron was the same as that of the Al2O3-based memristor synapse. In addition, we investigated the effect of negative-differential-resistance (NDR) characteristic on integrate property for our proposed neuron, depending on the compliance current level (i.e. a shape of metallic filaments in neuron device).The NDR slope was adjusted by varying a compliance current of a Al2O3-based cap-less conductive-bridge neuron. The current compliance (Icc) of 1 mA showed the NDR slope of ~ 0.56 decade/V, as shown in Fig. 1(b). For all spike amplitude (i.e. -0.6~-1.0 V), the resistances of neuron device abruptly increased at a certain number of spikes, depending on the spike amplitude, and then it gradually increased with the number of spikes, as shown in Fig. 1(c). In addition, the spike number being necessary for achieving ~600 Ω decreased exponentially with increasing the number of spikes, as showed integrate property depending on input spike amplitude, as shown in Fig. 1(d). Otherwise, the current compliance (Icc) of 0.1 mA, which was 10 times less than Fig 1 (b) presented the NDR slope of ~ 0.23 decade/V, which was 2 times less than Fig. 1(b), as shown in Fig. 1(e). For all spikes amplitude, the resistance of neuron devices gradually increased with the number of spikes, wherein the resistance of neuron devices increased with the spike amplitude (i.e. negative voltage pulse amplitude), as shown in Fig. 1(f). The spike number being necessary for achieving ~10 kΩ decreased exponentially with increasing the number of spikes, as shown in Fig. 1(g). Comparing Fig. 1(d) with Fig. 1(g), the variation of the spike number being necessary for achieving ~600 Ω for the NDR slope of ~-0.56 decade/V was much less that for the spike number being necessary for achieving ~10 kΩ for the NDR slope of ~-0.23 decade/V. This result indicates that, for the Al2O3-based cap-less conductive-bridge neuron, the NDR slope dominantly determines the integrate nature. In our presentation, we will discuss the mechanism why the integrate property depended on the NDR slope via understanding a shape of conductive-metallic-filaments in Al2O3 layer, which determine an integrate property of neuron devices. In particular, it will be reported that the shape of conductive-metallic-filaments strongly depended on the metal vacancy concentration in binary oxide (i.e. Al2O3) layer. Acknowledgement This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea Government (MSIT) (No. 2016M3A7B4910249). Reference "IEEE Transactions on Emerging Topics in Computational Intelligence," in IEEE Transactions on Emerging Topics in Computational Intelligence, vol. 2, no. 5, pp. C2-C2, Oct. 2018, doi: 10.1109/TETCI.2018.2867377.Jang, B. Attarimashalkoubeh, A. Prakash, H. Hwang and Y. Jeong, "Scalable Neuron Circuit Using Conductive-Bridge RAM for Pattern Reconstructions," in IEEE Transactions on Electron Devices, vol. 63, no. 6, pp. 2610-2613, June 2016, doi: 10.1109/TED.2016.2549359.Palma, M. Suri, D. Querlioz, E. Vianello and B. De Salvo, "Stochastic neuron design using conductive bridge RAM," 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Brooklyn, NY, 2013, pp. 95-100, doi: 10.1109/NanoArch.2013.6623051. Figure 1
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