Top Ge Layer Research Articles

Three-Layered Thin Films for Simultaneous Infrared Camouflage and Radiative Cooling.

With the rapid advancements in aerospace technology and infrared detection technology, there are increasing needs for materials with simultaneous infrared camouflage and radiative cooling capabilities. In this study, a three-layered Ge/Ag/Si thin film structure on a titanium alloy TC4 substrate (a widely used skin material for spacecraft) is designed and optimized to achieve such spectral compatibility by combining the transfer matrix method and the genetic algorithm. The structure exhibits a low average emissivity of 0.11 in the atmospheric windows of 3-5 μm and 8-14 μm for infrared camouflage and a high average emissivity of 0.69 in 5-8 μm for radiative cooling. Furthermore, the designed metasurface shows a high degree of robustness regarding the polarization and incidence angle of the incoming electromagnetic wave. The underlying mechanisms allowing for the spectral compatibility of the metasurface can be elucidated as follows: the top Ge layer selectively transmits electromagnetic waves ranging from 5-8 μm while it reflects those in the ranges of 3-5 μm and 8-14 μm. The transmitted electromagnetic waves from the Ge layer are first absorbed by the Ag layer and then localized in the Fabry-Perot resonance cavity formed by Ag layer, Si layer and TC4 substrate. Ag and TC4 make further intrinsic absorptions during the multiple reflections of the localized electromagnetic waves.

Fabrication of an atomically smooth Ge(111) surface by Au-induced crystallization at 170 °C

Crystalline Ge layer fabricated via layer-exchange metal-induced crystallization is a promising candidate as a seed layer for the epitaxial growth of III–V semiconductor thin films for multijunction solar cells. However, small crystalline islands that grow on top of the crystalline Ge layer are a problem, which roughens the surface and hinders subsequent epitaxial growth. Considering the effect of heating rate on the Au-induced crystallization behavior of Ge, it is found that the temperature required for the island growth in the top Ge layer was higher than that for the bottom layer. By carefully choosing the annealing conditions, the growth of the top Ge layer can be avoided resulting in an atomically smooth Ge(111) surface.

Electrically Tunable Ge/Si VIS-Swir Photodetector

Ge-on-Si photodiodes have been firstly reported more than twenty years ago opening the way for the integration of IR photodetectors on Si. A tremendous development has been done, moving from vertically illuminated, stand-alone devices, to waveguide integrated arrays of photodetectors and CMOS integrated imagers. Usually, the Ge epilayer act as the absorbing material for the NIR radiation, while Si acts only as a substrate. Here we report on a dual-band Ge-on-Si photodetector where light detection can take place both within the Ge epilayer and the underlying Si substrate: the device responsivity can thus be tuned from the VIS to the SWIR spectral range by means of an external bias. Therefore, the presented device can be implemented as a VIR-SWIR CMOS compatible imager.Two photodiodes in a back-to-back configuration are formed by p-doping the back side of a high resistivity Si wafer and by epitaxially growing a p-i-n heterojunction Ge-on-Si layer on the front side (Fig.1a)). An external bias can be applied to the whole layer stack by means of ohmic contacts formed on the top Ge layer and on the wafer backside (Fig.1b)). When a positive bias is applied between the top and bottom contact, the Ge diode is forward biased while the Si diode is reversed biased. In such a configuration the photocurrent generated within the Si substrate by back illuminating the device, will flow through the external circuit and be detected. By reversing the bias polarity, still maintaining a backside illumination, the photocurrent will be generated within the Ge epilayer: in this way it is possible to tune the device responsivity simply by controlling the external bias. A TCAD model has been set up to optimize doping levels, in particular that of the Si substrate, determining the most effective position the p-n junction within the Si photodiode and investigating the role played by substrate thickness[1].According with the simulation outcome, a p-type layer has been formed on the backside of an intrinsic Si wafer by spin-on-dopant obtaining a boron-doped layer with an average concentration of 2×1019cm-3 and a thickness of ≈300nm. The epitaxial growth has been performed by low-energy plasma-enhanced chemical vapor deposition (LEPECVD).Firstly, a 200nm thick phosphorous-doped Si layer has been deposited at 760°C followed by 3 µm thick nominally undoped Ge, grown at 500°C. Six thermal annealing cycles between 600-780°C have been performed in-situ to reduce the threading dislocation density. As a final step 150nm of boron-doped Ge have been deposited.Ge mesas with dimensions ranging between 100-500µm have been realized by standard UV-lithography and dry etching on the Ge-on-Si epitaxial layer. The mesas have been etched down to the intrinsic Si surface to electrically isolate the different devices on the same chip. The top ohmic contacts have been realized by e-beam deposition of a Ti/Al metal stack and lift-off. Different bottom ohmic contact have been tested both by depositing two rectangular stripes of Ti/Au or by depositing a transparent ITO layer on the backside of the chip.Optical characterization was performed by means of a lamp-monochromator set-up. The VIS/SWIR bias dependent dual-band operation of the device is demonstrated in Fig.1c), where the spectral responsivity is shown for two different applied voltages. The peak responsivities are 0.41A/W and 0.63A/W at 960nm and 1520nm, respectively. The specific detectivity D* of the device has been found to be 7·1011cmHz1/2/W and 2·1010cmHz1/2/W in the VIS and NIR, respectively[2].VIS-SWIR single-pixel imaging was performed by mounting the chip on a rastering system comprising a three-axis stage. In this way the pixel can scan the image plane behind a piano-convex lens. Two images, one in the VIS and one in the SWIR, can be obtained by repeating the scanning and changing the polarity of the applied bias at the device Fig.4d). A coloured VIS image has been obtained by repeating the measurements three times with three different optical bandpass filters (450nm, 550nm and 650nm) resulting in three images with R, G, and B components, which have been combined to obtain the final VIS image.In conclusion, we have designed and fabricated a voltage-tunable dual-band photodetector operating in the VIS and SWIR range. The device is based on a couple of p-i-n photodiodes connected back-to-back formed within a Ge-on-Si epitaxial structure. The device architecture enables to electronically select the shorter (400-1100nm) or longer (1000-1600nm) wavelength range with a relatively low applied voltage. VIS-SWIR single-pixel imaging has been performed.[1] A.De Iacovo, et al., Journal of Lightwave Technology, 37(14), 3517(2019).[2] E.Talamas Simola, et al., Opt. Express 27, 8529-8539(2019). Figure 1

Strain Modulation of Selectively and/or Globally Grown Ge Layers.

This article presents a novel method to grow a high-quality compressive-strain Ge epilayer on Si using the selective epitaxial growth (SEG) applying the RPCVD technique. The procedures are composed of a global growth of Ge layer on Si followed by a planarization using CMP as initial process steps. The growth parameters of the Ge layer were carefully optimized and after cycle-annealing treatments, the threading dislocation density (TDD) was reduced to 3 × 107 cm−2. As a result of this process, a tensile strain of 0.25% was induced, whereas the RMS value was as low as 0.81 nm. Later, these substrates were covered by an oxide layer and patterned to create trenches for selective epitaxy growth (SEG) of the Ge layer. In these structures, a type of compressive strain was formed in the SEG Ge top layer. The strain amount was −0.34%; meanwhile, the TDD and RMS surface roughness were 2 × 106 cm−2 and 0.68 nm, respectively. HRXRD and TEM results also verified the existence of compressive strain in selectively grown Ge layer. In contrast to the tensile strained Ge layer (globally grown), enhanced PL intensity by a factor of more than 2 is partially due to the improved material quality. The significantly high PL intensity is attributed to the improved crystalline quality of the selectively grown Ge layer. The change in direct bandgap energy of PL was observed, owing to the compressive strain introduced. Hall measurement shows that a selectively grown Ge layer possesses room temperature hole mobility up to 375 cm2/Vs, which is approximately 3 times larger than that of the Ge (132 cm2/Vs). Our work offers fundamental guidance for the growth of high-quality and compressive strain Ge epilayer on Si for future Ge-based optoelectronics integration applications.

Phase Transformation in Germanium-on-Insulator (GeOI) Films Using Raman Spectroscopy and Nanoindentation

Germanium-on-insulator (GeOI) films fabricated using the SMART CUT wafer bonding and film exfoliation technology were investigated for the mechanical properties and induced phase transformations by using nanoindentation and Raman spectroscopy experiments. The hardness and modulus results of the GeOI films are significantly different from the published SOI literature and bulk germanium results obtained by Liu et al., 2020 [1] and SOI films results obtained by Miller et al., 2007 [2]. From our measured hardness results of 8 to 10 GPa for very thin single crystal Ge(100) films compared to 13.1 GPa for Bulk Ge (100), one can conclude that the thinning of crystalline Ge films leads to a considerable softening of the crystalline Ge resulting in less brittle robust films. Similarly, our measured modulus of 130 to 140 GPa for thin Ge (100) films compared to the reported bulk Ge (100) value of 157 GPa corroborates these research findings. The GeOI films are softer and more flexible as compared to bulk Ge hardness and stiffness properties. The Raman spectroscopy of the spherical indents indicate bands of metastable Ge phases @ 220 cm-1, 195 cm-1 and 184 cm-1 wavenumbers. Our results demonstrate that a spherical indenter impacted a wider area of contact and produced GeOI indented surfaces free of cracks and fracture. The spherical indenter tip kept the Ge top layer intact when compared to the Berkovich indenter tip during penetration. In contrast, the Berkovich indenter tip developed excessive fracture that resulted in displacing the Ge top layer sideways and exposed the Si substrate underneath revealing Raman spectra bands of metastable Si phases @ 350 cm-1, 399 cm-1 and 430 cm-1.Apart from the well documented electrical advantages of GeOI, the reported research on the nanomechanical properties reveals considerable softening and flexibility of the very thin exfoliated single crystal Ge films that promise added benefits and further implications for enhancing potential device application of GeOI wafers for process integration.1.] N. Liu, X-J Yang, Z. Yu, and L. Zhao, Trans. Nonferrous Met. Soc. China, 30, 181 (2020).2.] N. Miller, K. Tapily, H. Baumgart, G.K. Celler, F. Brunier, and A.A. Elmustafa, Mater. Res. Soc. Symp. Proc. Vol. 1021 © 2007 Materials Research Society, 1021-HH05-24. Boston, Massachusetts. (2007).

Evaluation of the mechanical properties of germanium-on-insulator (GeOI) films by Raman spectroscopy and nanoindentation

Germanium-on-insulator (GeOI) films fabricated using the Smart Cut™ wafer bonding and film exfoliation technology were investigated for the mechanical properties and induced phase transformations by using nanoindentation and Raman spectroscopy experiments. The hardness and modulus results of the GeOI films are significantly different from the literature published Silicon-on-Insulator and bulk germanium results. The GeOI films are softer and more flexible as compared to bulk Ge hardness and stiffness properties. The Raman spectroscopy of the spherical indents indicates bands of metastable Ge phases @ 220 cm−1, 195 cm−1, and 184 cm−1 wavenumbers. Our results demonstrate that a spherical indenter impacted a wider area of contact and produced GeOI indented surfaces free of cracks and fracture. The spherical indenter tip kept the Ge top layer intact when compared to the Berkovich indenter tip during penetration. In contrast, the Berkovich indenter tip developed excessive fracture that resulted in displacing the Ge top layer sideways and exposed the Si substrate underneath revealing Raman spectra bands of metastable Si phases @ 350 cm−1, 399 cm−1, and 430 cm−1.

Fabrication of Germanium-on-insulator in a Ge wafer with a crystalline Ge top layer and buried GeO2 layer by oxygen ion implantation

The paper reports fabrication of Germanium-on-Insulator (GeOI) wafer by Oxygen ion implantation of an undoped Ge wafer of orientation (100). O+ ions (energy 200 keV) were implanted to a fluence of 1.9 × 1018 ions-cm−2 and the implanted wafer was subjected to Rapid Thermal Annealing. The resulting wafer has a top crystalline Ge layer of ~ 220 nm thickness and resistivity ≈32 Ohm-cm and a buried Oxide layer (BOX) of crystalline GeO2 (thickness ≈0.62 μm). The crystalline GeO2 layer has hexagonal crystal structure with lattice constants close to the standard values. Raman Spectroscopy and cross-sectional electron microscopy established that the top Ge layer was recrystallized during annealing with a residual tensile strain of around +0.4% and an estimated dislocation density of 2.7 × 107cm−2. The crystallinity and electrical characteristics of the top layer and the quality of the BOX layer are such that it can be utilized for device fabrication.

Fabrication and characterization of sensitive vertical P-i-N germanium photodiodes as infrared detectors

Germanium on silicon P-i-N photodetectors fabricated using standard CMOS tools are now successfully used as uncooled detectors in the near-infrared (NIR), which extends from 0.75 to 1.4 μm and in the short-wave infrared (SWIR), which extends from 1.4 to 3 μm. They feature a remarkably high responsivity up to 1550 nm and a low dark current when they are operated at reverse biases. The aim is to achieve a very low dark current density and a high responsivity with a small Germanium photodiode pitch. In this paper we discuss the fabrication and the characterization of vertical P-i-N photodiodes with the epitaxy of Germanium on Silicon. The Germanium epilayer is a 1.3 μm thick Ge film with a bottom Ge layer P-type doped with boron at 1019 cm−3 and a top Ge layer N-type doped with phosphorus at 1020 cm−3. Secondary ion mass spectroscopy was used to assess the doping level of the Phosphorus doped N + region. The strain in the Germanium epilayer on Silicon substrate was investigated. It was tensile, with a value around +0.15% from x-ray diffraction (XRD), in good agreement with a +0.12% value from Raman spectroscopy. In this paper, we focus on P-i-N photodiodes with a circular shape and a diameter of 10 μm. Electrical characterizations were performed in dark and under NIR-SWIR radiation (1310 nm, 1550 nm), with very low dark current of 0.45 nA and enhanced photocurrent at −1 V. The external responsivities were measured at 0.275 and 0.133 A W−1 for 1310 nm and 1550 nm, respectively. Finally, internal quantum efficiencies of the fabricated vertical P-i-N photodiodes were extracted at 66% and 52% at 1310 nm and 1550 nm, respectively, in good agreement with TCAD simulations. Finally, a measurement of the noise in dark conditions is presented.

Integrating GeSn photodiode on a 200 mm Ge-on-insulator photonics platform with Ge CMOS devices for advanced OEIC operating at 2 μm band.

High-performance GeSn multiple-quantum-well (MQW) photodiode is demonstrated on a 200 mm Ge-on-insulator (GeOI) photonics platform for the first time. Both GeSn MQW active layer stack and Ge layer (top Ge layer of GeOI after bonding) were grown using a single epitaxy step on a standard (001)-oriented Si substrate (donor wafer) using a reduced pressure chemical vapor deposition (RPCVD). Direct wafer bonding and layer transfer technique were then employed to transfer the GeSn MQW device layers and Ge layer to a 200 mm SiO2-terminated Si handle substrate. The surface illuminated GeSn MQW photodiode realized on this platform exhibits an ultra-low leakage current density of 25 mA/cm2 at room temperature and an enhanced photo sensitivity at 2 μm of 30 mA/W as compared to a GeSn MQW photodiode on Si at 2 μm. The underlying GeOI platform enables monolithic integration of a complete suite of photonics devices operating at 2 μm band, including GeOI strip waveguides, grating couplers, micro-ring modulators, Mach-Zehnder interferometer modulators, etc. In addition, Ge CMOS circuits can also be realized on this common platform using a "photonic-first and electronic-last" processing approach. In this work, as prototype demonstration, both Ge p- and n-channel fin field-effect transistors (FinFETs) were realized on GeOI simultaneously with decent static electrical characteristics. Subthreshold swings of 150 and 99 mV/decade at |VD| = 0.1 V and drive currents of 91 and 10.3 μA/μm at |VG-VTH| = 1 V and |VD| = 0.75 V were achieved for p- and n-FinFETs, respectively. This works illustrates the potential of integrating GeSn (as photo detection material) on GeOI platform for Ge-based optoelectronics integrated circuits (OEICs) targeting communication applications at 2 μm band.

Effect of Ge Thin Layer Position on Formation and Property of CZTSSe Thin Films and Solar Cells Prepared by Sputtering Method

In this work we deposited a Ge thin layer under or upon Cu-Zn-Sn-S precursor by sputtering, followed by selenization process to obtain Ge doped CZTSSe thin films. A comparison of structural, morphology and optoelectrical property on Ge doped CZTSSe thin films with different Ge layer position was studied. It was found that even a little amount of Ge doping could affect the crystallization of CZTSSe grains. The solar cells based on two kinds of precursors both had VOC improvement compared with undoped CZTSSe solar cell. However, due to the inner stress in CZTSSe thin film, cracks appeared between the interface of buffer layer and window layer in CZTSSe solar cell with Ge bottom layer, leading to the decrease of conversion efficiency. With the help of Ge in reducing bulk recombination, CZTSSe solar cell based on Cu-Zn-Sn-S precursor with Ge top layer had a conversion efficiency of 5.38%, in contrast to 3.01% and 4.30% of CZTSSe solar cell with Ge bottom layer and undoped CZTSSe solar cell, respectively.

(Invited) Anisotropic Strain Introduction into Si/Ge Hetero Structures

Ge is one of the most attractive materials toward ultra-low-power and high-performance complementary metal oxide semiconductor (CMOS) circuits owing to its higher hole mobility than Si and various III-V materials. Moreover, it is possible to enhance the mobility further by introducing strain into the channel. Especially an uniaxial strain is expected to provide the highest hole mobility [1,2]. So far, several approaches have been researched to create uniaxially strained SiGe and Ge channels. We have been developing the selective ion implantation technique to induce uniaxial strain into SiGe buffer layers [3,4]. In this method, a Si substrate is selectively subjected to the ion implantation and followed by the SiGe overgrowth. A subsequent post-growth-annealing promotes the strain relaxation of the SiGe selectively in the implanted region as the implantation-induced defects formed act as dislocation nucleation sources. And hence, with proper configurations of the selective implantation, the anisotropic strain can be induced in the SiGe in the unimplanted area since the neighboring relaxed SiGe films in the ion-implanted areas provide shear stress at the interfaces. In previous works, we succeeded in fabrication of uniaxially strained SiGe buffer layers with Ge concentrations below 30% [3,4], which can serve as proper templates for uniaxially strained Si/Ge heterostructures, such as uniaxially strained Si and Si1-xGex (x < 0.5) channels. For the formation of uniaxially strained Ge and Si1-xGex(x > 0.5) channels, however, SiGe buffers with higher Ge concentrations are required. In this study, therefore, we fabricate uniaxially strained SiGe buffer layers with high Ge concentrations with the selective ion implantation technique and overgrew uniaxially strained Ge layers on the SiGe buffers. The sample fabrication procedure is as follows (Fig.1). Ar+ ions were selectively implanted into the Ge substrate through the SiO2 mask window. Line widths of the ion-implanted and unimplanted regions were varied from 2 to 20 μm. A SiGe layer was pseudomorphically grown on the selectively ion-implanted Ge substrate with solid source molecular beam epitaxy. Subsequently, postgrowth annealing was carried out to promote the strain relaxation of the SiGe only in the implanted region. Finally a Ge layer with the thickness of 10 nm was pseudomorphically grown on the SiGe. Figure 2 shows a Raman mapping image for the sample with 3-μm-width stripe lines, where a Ge-Ge mode peak wavenumbers obtained from the top Ge layer were scanned. A clear contrast is observed corresponding to the large and small compressive strain of the Ge layer in the implanted and unimplanted regions, respectively. This demonstrates that the strain of the Ge is laterally controlled by the selective implantation. Since XRD measurements confirmed that the SiGe buffer layer has uniaxial strain, it can be said that the top Ge layer is also uniaxially strained. This uniaxially strained Ge layer can be transferred onto the insulator substrate via wafer bonding process, where the ion-implanted defective region can be removed. Finally defect-free uniaxially strained GOI substrate can be obtained, which is applicable to high mobility uniaxilly strained Ge channel MOSFETs. [1] Y. Sun, et al., J. Appl. Phys. 101, 104503 (2007). [2] T. Krishnamohan et al., IEDM Tech. Dig., 899 (2008). [3] K. Sawano et al., Appl.Phys.Express 1, 121401 (2008). [4] K. Sawano et al., J. of Crystal Growth 378, 251 (2013). Figure 1

Fabrication of Relaxed Germanium on Insulator via Room Temperature Wafer Bonding

Germanium with higher electron and hole mobilities has been considered as a potential material for replacement of Si in CMOS transistors. However, due to the lower band gap of Ge compare to Si, bulk Ge devices suffer a high leakage current, which could be suppressed by employing a germanium on insulator (GeOI) substrate. High-κ-all-around asymmetrically-strained germanium nanowire trigate p-MOSFETs have exhibited the highest hole mobility recorded (1490 cm2/V.s) [1]. There are several approaches for the fabrication of GeOI substrates including separation-by-implanted-oxygen (SIMOX) [2], Ge condensation [3], liquid phase epitaxy [4], and wafer bonding [5]. Wafer bonding technique is advantageous among the other techniques due to its simplicity and potential for achieving high quality crystalline Ge layer.In this work we present a method to fabricate relaxed and strained GeOI substrates using heteroepitaxy and layer transfer techniques. The goal is to produce high quality wafer scale GeOI platform for relaxed and strained Ge nanowire CMOS fabrication. GeOI substrates are designed and fabricated via wafer bonding and etch back process without intermediary chemical mechanical polishing (CMP) step. Low temperature bonding avoids strain relaxation, Ge diffusion and detaching due to thermal expansion coefficient differences. In this design, GeOI structure is achieved by epitaxial growth and conventional dry and wet-etch techniques. All the epitaxial layers in the process are grown using RPCVD Epsilon 2000 ASM reactor. The fabrication process for both structures starts with the epitaxial growth of a roughly 1 µm Si0.96Ge0.04 etch stop layer. In the strained GeOI design the process is followed by epitaxial growth of an intermediate relaxed SiGe buffer with a Ge content of 40-50 percent, then a strained Si etch-stop layer and finally pseudomorphic growth of a thin strained Ge layer on top (Fig. 1). In relaxed GeOI structure on 1 µm Si0.96Ge0.04 etch stop layer a rather thick Ge layer (~300 nm) is grown in two steps, first a low temperature (LT) Ge is grown with high defect density and then a high temperature (HT) high quality Ge layer is grown on top (Fig. 2). Once the epitaxial growth of the structures is finished, 10 nm Al2O3 is deposited on top the Ge layer using atomic layer deposition (ALD). Then the wafers are brought together in the atmosphere pressure for room temperature bonding. The etch-back process begins by thinning down the donor wafer using Applied Materials Centura deep trench Si etch chamber (etch rate ~7 µm/min ). The etching process stops on the Si0.96Ge0.04 etch stop layer using endpoint detection system. At that point, the Si0.96Ge0.04etch-stop layer is selectively etched in TMAH solution. Then in relaxed GeOI structure the 300 nm Ge layer is oxidized and chemically thinned, up to the desired thickness (Fig. 2). In the strained GeOI structure SiGe relaxed buffer layer is selectively wet etched using dHF(100H2O:1HF):HNO3:CH3COOH (0.15:0.20:0.30) solution, and the strained Si layer is selectively removed in TMAH solution, leaving the strained Ge layer on Al2O3 (Fig. 1). Infrared (IR) image of the bonded wafers shows few voids at the interface and the bonding can withstand fast deep Si dry etching. X-ray analysis shows high quality well separated peaks for both structures and demonstrates the strain in top Ge layer (for the strained GeOI). The bonding strength will be measured using stress tester. The bonded interfaces will be observed by high resolution transmission electron microscopy (HRTEM). Topology of both Ge surfaces will be shown by atomic force microscopy (AFM).In summary, processes for the fabrication of high quality, low defect, monocrystalline, relaxed and strained germanium on insulator substrates are developed and optimized. This technique can serve as a platform for the fabrication of high performance Ge devices. AcknowledgmentThis work was supported by European Union ERC Advanced Grant 228229 OSIRIS.Fig. 1) schematic image of the bond and etch back process for strained GeOIFig. 2) schematic image of the bond and etch back process for relaxed GeOI[1] J. L. H. et al., IEEE, p. 4, 2012.[2] T. Mizuno, et al., IEEE Electron Device Lett., no. 5, pp. 230–232, May 2000.[3] T. Tezuka, et al., Appl. Phys. Lett., no. 12, p. 1798, 2001.[4] M. Miyao, et al., Appl. Phys. Express, p. 045503, Apr. 2009.[5] G. Taraschi, et al., Solid. State. Electron., no. 8, pp. 1297–1305, Aug. 2004.

Double-Layered Ge Thin Films on Insulators Formed by an Al-Induced Layer-Exchange Process

A large-grained (111)-oriented Ge thin film is achieved on a SiO2 glass substrate using an Al-induced crystallization (AIC) technique. Low-temperature (350 °C) AIC of an amorphous Ge thin film (50 nm thickness) resulted in a self-organized double-layered structure of polycrystalline Ge layers. The top Ge layer consisted of randomly oriented small grains (1 μm diameter) with a high defect density; in contrast, the bottom Ge layer was of high quality. Based on the growth model, we annihilated the top Ge layer using preferential etching. The bared bottom Ge layer provided a (111)-oriented area fraction of 99% and an average grain size of 90 μm. This Ge layer appears promising for use in Ge-based thin-film devices, as well as a heteroepitaxial seed layer for group III–V compound semiconductors, aligned nanowires, and other advanced materials.

Doppler Broadening Spectroscopy of Positron Annihilation near Ge and Si (001) Single Crystal Surfaces

carrier mobility compared with Si. 1 Although closely related to Si, in some aspects Ge shows a quite different behavior. This should be taken into account when processing steps are developed for the production of electronic devices with active Ge layers, in which the Ge layer surfaces and interfaces will play an important role. 2 In this letter, we investigated the effect of the free (001) surface on positron annihilation spectroscopy (PAS) results, comparing Si and Ge substrates. PAS is a powerful tool for the study of vacancy-type defects in semiconductors, 3,4 e.g. in irradiated Si and Ge. Positron trapping at vacancies can be observed by the narrowing of the Doppler-broadened 511 keV annihilation γ-ray peak. By varying the incident positron energy, one can probe different sample depths in the submicron range. This method is called Doppler Broadening Spectroscopy (DBS). The so called S-parameter, extracted from DBS, corresponds to positron annihilation by the valence electrons and is sensitive to open volume defects. An increase of the S-parameter can be simply interpreted as an increase of the number of vacancy-type defects. The S-parameter obtained for an incident positron energy lower than 2 keV, however, in general differs from the one obtained for positron energies above 15 keV. Incident positrons with lower energy will indeed mainly interact with the near surface area of the sample, and will be sensitive for thin native oxide layers, surface contamination, surface roughness, surface defects, etc. The S-parameter decreases in general toward the surface for most materials due to positron diffusion toward and annihilation at the surface. 5 The present letter reports on the different behavior of Si and Ge with this respect. While in case of Si, the S-parameter decreases considerably near the Si (001) surface as expected and as is the case for other semiconductor materials, in the case of a Ge (001) surface, the S-parameter shows no remarkable dependence on depth although both are group IV elements and have the same diamond structure. For the PAS measurements, moderately doped p-type Si and n-type Ge (001) wafers were used with a resistivity at room temperature in the range of 10–100 ohm corresponding with a carrier concentration at room temperature in the range of 10 13 ∼10 15 cm −3 . As a reference for the Si bulk and at the same time the near surface of Ge, a Geon-Insulator (GOI) wafer with a un-doped Ge top-layer produced by the Ge condensation technique, was also included in the study. The carrier concentration in the n-type Ge film of the GOI wafer that

Ultra-smooth epitaxial Ge grown on Si(001) utilizing a thin C-doped Ge buffer layer

Here, we present work on epitaxial Ge films grown on a thin buffer layer of C doped Ge (Ge:C). The growth rate of Ge:C is found to slow over time and is thus unsuitable for thick (&amp;gt;20 nm) layers. We demonstrate Ge films from 10 nm to &amp;gt;150 nm are possible by growing pure Ge on a thin Ge:C buffer. It is shown that this stack yields exceedingly low roughness levels (comparable to bulk Si wafers) and contains fewer defects and higher Hall mobility compared to traditional heteroepitaxial Ge. The addition of C at the interface helps reduce strain by its smaller atomic radius and its ability to pin defects within the thin buffer layer that do not thread to the top Ge layer.

Initial stage growth of GexSi1-x layers and Ge quantum dot formation on GexSi1-x surface by MBE.

Critical thicknesses of two-dimensional to three-dimensional growth in GexSi1−x layers were measured as a function of composition for different growth temperatures. In addition to the (2 × 1) superstructure for a Ge film grown on Si(100), the GexSi1−x layers are characterized by the formation of (2 × n) reconstruction. We measured n for all layers of Ge/GexSi1−x/Ge heterosystem using our software with respect to the video recording of reflection high-energy electron diffraction (RHEED) pattern during growth. The n reaches a minimum value of about 8 for clear Ge layer, whereas for GexSi1−x films, n is increased from 8 to 14. The presence of a thin strained film of the GexSi1−x caused not only the changes in critical thicknesses of the transitions, but also affected the properties of the germanium nanocluster array for the top Ge layer. Based on the RHEED data, the hut-like island form, which has not been previously observed by us between the hut and dome islands, has been detected. Data on the growth of Ge/GexSi1−x/Ge heterostructures with the uniform array of islands in the second layer of the Ge film have been received.

Enhanced operation and retention characteristics in charge-trapping flash memory device with a novel Si/Ge super-lattice channel

Charge-trapping flash memory devices with super-lattice channels having different stacking structures and thicknesses of Ge top-layer are investigated in this work. Both programming and erasing speeds are significantly improved for devices with super-lattice channels. Programming speed increases with increasing thickness of Ge layer in the super-lattice channel. The enhancement on programming speed can be achieved up to 40 times or better. For devices with Ge top-layer on super-lattice channel, a further enhancement is observed with increasing Ge thickness. The retention characteristic of devices with super-lattice channel is better than that with Si-channel devices owing to the slightly increased thickness of tunneling oxide.

Growth of Ge quantum dot mediated by boron on Ge wetting layer

We report on the influence of boron on the formation of Ge quantum dots. The investigated structure consists of a Ge wetting layer, on which a sub-monolayer boron is deposited and subsequently a Ge top layer. For sufficiently thin Ge top layers, the strain field induced by boron on Ge wetting layer destabilizes the Ge top layer and causes the formation of small Ge quantum dots. However, for thicker Ge top layers, boron on the Ge wetting layer diffuses into Ge layers, compensates partly the strain and delays the evolution of Ge quantum dots. By this method, small Ge quantum dots with high density as well as size uniformity can be formed by optimizing the growth condition.

A GeSi-buffer structure for growth of high-quality GaAs epitaxial layers on a Si substrate

A SiGe-buffer structure for growth of high-quality GaAs layers on a Si (100) substrate is proposed. For the growth of this SiGe-buffer structure, a 0.8-µm Si0.1 Ge0.9 layer was first grown. Because of the large mismatch between this layer and the Si substrate, many dislocations formed near the interface and in the low part of the Si0.1Ge0.9 layer. A 0.8-µm Si0.05Ge0.95 layer and a 1-µm top Ge layer were subsequently grown. The strained Si0.05Ge0.95/Si0.1Ge0.9 and Ge/Si0.05Ge0.95 interfaces formed can bend and terminate the upward-propagated dislocations very effectively. An in-situ annealing process is also performed for each individual layer. Finally, a 1–3-µm GaAs film was grown by metal-organic chemical vapor deposition (MOCVD) at 600°C. The experimental results show that the dislocation density in the top Ge and GaAs layers can be greatly reduced, and the surface was kept very smooth after growth, while the total thickness of the structure was only 5.1 µm (2.6-µm SiGe-buffer structure +2.5-µm GaAs layer).

Growth of high quality Ge epitaxial layer on Si(100) substrate using ultra thin Si0.5Ge0.5 buffer

ABSTRACTMethods for forming Ge epitaxial layer on Si (100) substrate have been vigorously sought due to potential applications of such structure as a virtual substrate for III-V devices on Si. Various methods were proposed to realize low threading dislocation density and smooth surface. To date, such methods involve more than one of thick (micrometer order) SiGe buffer growth process, high temperature annealing steps and CMP process, which could compromise reliability and suitability for production.In this study, we report feasibility of a thin (in the order of 10nm) SiGe buffer layer to realize pure Ge epitaxial layer with good crystalinity, low threading dislocation density, and smooth surface without high temperature annealing steps and CMP process.As a result, we achieved shorter time for growth of practical thickness of crystalline Ge on Si (100) substrate, and also get the high quality Ge epitaxial layer which has low threading dislocation density with very smooth surface.Ge epitaxial layer and underlying thin SixGe1−x buffer layer were grown on Si (100) substrate using a cold wall UHV-CVD system. Source gases of Si and Ge were Si2H6 and GeH4, respectively. No carrier gas was used for this process. SiGe buffer layer was grown on Si(100) substrate at 450 – 520˚C. Two-step growth process was employed to grow Ge epitaxial layer on the buffer layer. Ge seed layer was grown at a low temperature (350–400˚C), followed by Ge thick layer growth at a high temperature (550–650˚C). XRD, TEM, EPD, and AFM were used for characterization of Ge epitaxial layer.Optimization of growth temperature and source gas flow rate ratio enabled to obtain an effective buffer layer thinner than 10nm. The thin buffer layer realizes process time shortening, which is within 10min, and the smooth surface is realized without crosshatch structure. The buffer thickness is 1/160 to 1/1000 than that of previously known methods using thick SiGe buffer layers. Thin SiGe buffer also enabled process time shortening for Ge seed layer growth as two-dimensional Ge layer was formed faster on the thin SiGe buffer layer than on Si. XRD of the Ge seed layer showed 97% relaxation as grown and fully relaxed at 550˚C. The threading dislocation density of the top Ge layer was estimated below 1E7counts/cm2 by TEM and EPD.The misfit dislocations oriented along [110] at the interface between the SiGe buffer layer and the Ge layer and the distances are 9.5nm constantly in cross-sectional TEM image. We are checking the surface roughness of the Ge epitaxial layer by using AFM.