TMS320C80 Multimedia Video Processor Research Articles

Real-Time Implementation of the Relative Position Estimation Algorithm Using the Aerial Image Sequence

This paper deals with an implementation of the navigation parameter extraction algorithm on the TMS320C80 multimedia video processor (MVP). Especially, this paper focuses on the relative position estimation algorithm which plays an important role in the real-time operation of the overall system. Based on the relative position estimation algorithm proposed in [1], we develop a sliding window method that can reduce the computational complexity of the feature block extraction greatly. Then, we make the algorithm fit into four fixed-point processors in the MVP, considering the data dependency and the effects due to the finite register length. As a result, we demonstrate that the navigation parameter extraction system implemented on the MVP can operate at full-frame rate, by exploiting the computational power of the MVP fully.

Interactive Image Morphing on a Single-Chip Multiprocessor using a Multilayered Parallel Image Computing Library

Image morphing uses a combination of warping and image interpolation to produce a gradual visual transformation of one image into another. Due to the complexity of the operations involved in warping, creating the intermediate images that compose a “morph” is computationally intensive. Prior implementations have been slow, taking several seconds or even minutes, to compute each intermediate image. By optimizing the morphing algorithm for use on the Texas Instruments TMS320C80 Multimedia Video Processor (MVP), we have achieved interactive image morphing, which can compute an intermediate image in less than 200 ms. Using the University of Washington Image Computing Library (UWICL) for the MVP, a multilayered parallel image computing library, we were able to implement our interactive morphing algorithm with a minimum amount of programming effort. Thus, in addition to being significantly faster, our implementation is an excellent demonstration of the capability and development potential of the MVP and UWICL combination in higher-level algorithms and applications.

DSP-based system for real-time video communications

This article describes the architecture of a digital signal processor (DSP)-based real-time video communications system and the implementation of the ITU-T H.263 video coding standard on the system. The system incorporates a Texas Instruments TMS320C80 Multimedia Video Processor (MVP), a high-performance, single-chip multiprocessor-based DSP that is optimized for image and video operations. Our implementation of the ITU-T H.263 is optimized to make full use of the special features of the TMS320C80 MVP. The various related processing tasks have been efficiently distributed on the parallel processing elements within the TMS320C80 MVP. © 1999 John Wiley & Sons, Inc. Int J Imaging Syst Technol 10: 47–53, 1999

Interactive three-dimensional ultrasound using a programmable multimedia processor

We developed an interactive three-dimensional (3D) ultrasound (US) workstation that is inexpensive and suitable for use in research and clinical environments. Our personal computer–based system produces 3D volumes by acquiring a series of 2D images from a commercial ultrasound scanner, spatially registering the images using an electromagnetic position sensor, and reconstructing the data into a regular 3D Cartesian volume. The 3D US system uses an imaging board based on the Texas Instruments TMS320C80 Multimedia Video Processor (MVP), a fully programmable mediaprocessor that includes multiple processing units on a single chip. We developed efficient volume reconstruction and visualization algorithms for the MVP that allow our 3D US system to provide the same immediate feedback as current 2D US technologies with the added advantage of presenting information in three dimensions. For example, for acquired sequences of 512 × 512 US images, volumes can be reconstructed using six degree-of-freedom position measurements at 11.4 frames/s. A modified reconstruction algorithm that performs incremental reconstruction was developed to enable real-time volume reconstruction and visualization during acquisition and operates at 12.5 frames/s. US volumes can be rendered via shear-warp factorization and maximum intensity projection (MIP) at 10 frames/s for 128 × 128 × 128 volumes and 1.45 frames/s for 255 × 255 × 255 volumes. © 1998 John Wiley & Sons, Inc. Int J Imaging Syst Technol 9: 442–454, 1998

Generalized image warping using enhanced lookup tables

Image warping includes a wide variety of algorithms used in the spatial transformation of images. Warping typically involves a geometric transformation governed by a set of polynomial equations followed by some form of interpolation. When the geometric transformation does not change from one image to the next, or a more generalized warp is desired, a spatial lookup table (LUT) composed of precalculated inverse (or forward) mapping coordinates has been used instead of performing the same geometric transformation on every image. This article presents an algorithm that takes the LUT approach one step further. It uses an enhanced LUT (ELUT) that incorporates precomputed data transfer and interpolation information. Once computed, it speeds up processing by making data transfers more efficient and eliminating the need for the pixel address and interpolation coefficient calculations. This article also describes the implementation of ELUT-based image warping on the high-performance TMS320C80 Multimedia Video Processor (MVP). To produce an interesting and difficult generalized warp on a 512 × 512 8-bit gray-scale and 32-bit color image, it takes only 15.1 and 32.4 ms, respectively. © 1998 John Wiley & Sons, Inc. Int J Imaging Syst Technol 9: 475–483, 1998

Performance analysis and tuning for a single-chip multiprocessor DSP

A new generation of high performance programmable digital signal processors has a highly integrated parallel architecture, incorporating special purpose hardware features, on-chip memory, and multiple processors into a single chip. Such single chip multiprocessor DSPs, however, require a sophisticated performance monitoring tool to achieve maximum performance. The authors discuss the requirements and functionality of performance monitoring tools suitable for single chip multiprocessor DSPs. Specifically, they describe a performance monitoring tool that satisfies these requirements and functionality: the MVP Performance Monitor, developed for the Texas Instruments' TMS320C80 Multimedia Video Processor. They present an overview of the MPM and a general performance tuning approach using the MPM. An 8/spl times/8 block based 2D discrete cosine transform (DCT) implementation demonstrates the MPM's effectiveness. The authors achieved an overall speedup of 4.67 by tuning the performance based on the monitoring results from the MPM.

A Real-Time Scan Conversion Algorithm on Commercially Available Microprocessors1

We have developed a new ultrasound scan conversion algorithm that can be executed very efficiently on modern microprocessors. Our algorithm is designed to handle the address calculations and input and output (I/O) data loading concurrently with the interpolation. The processing unit's computing power can be dedicated to performing pixel interpolations while the other operations are handled by an independent direct memory access (DMA) controller. By making intelligent use of the I/O transfer capabilities of the DMA controller, the algorithm avoids spending the processing unit's valuable computing cycles in address calculations and nonactive pixel blanking. Furthermore, the new approach speeds up the computation by utilizing the ability of superscalar and very long instruction word (VLIW) processors to perform multiple operations in parallel. Our scan conversion algorithm was implemented on a multimedia and imaging system based on the Texas Instruments TMS320C80 Multimedia Video Processor (MVP). Computing cycles are spent only on predeterminable nonzero output pixels. For example, an execution time of 11.4 ms was achieved when there are 101,829 nonzero output pixels. This algorithm demonstrates a substantial improvement over previous scan conversion algorithms, and its optimized implementation enables modern commercially available programmable processors to support scan conversion at video rates.

A real-time scan conversion algorithm on commercially available microprocessors.

We have developed a new ultrasound scan conversion algorithm that can be executed very efficiently on modern microprocessors. Our algorithm is designed to handle the address calculations and input and output (I/O) data loading concurrently with the interpolation. The processing unit's computing power can be dedicated to performing pixel interpolations while the other operations are handled by an independent direct memory access (DMA) controller. By making intelligent use of the I/O transfer capabilities of the DMA controller, the algorithm avoids spending the processing unit's valuable computing cycles in address calculations and nonactive pixel blanking. Furthermore, the new approach speeds up the computation by utilizing the ability of superscalar and very long instruction word (VLIW) processors to perform multiple operations in parallel. Our scan conversion algorithm was implemented on a multimedia and imaging system based on the Texas Instruments TMS320C80 Multimedia Video Processor (MVP). Computing cycles are spent only on predeterminable nonzero output pixels. For example, an execution time of 11.4 ms was achieved when there are 101,829 nonzero output pixels. This algorithm demonstrates a substantial improvement over previous scan conversion algorithms, and its optimized implementation enables modern commercially available programmable processors to support scan conversion at video rates.