TLC NAND Flash Research Articles

DMMC: A Polar Code Construction Method for Improving Performance in TLC NAND Flash

3D TLC NAND flash memory significantly increases the storage capacity but makes data more prone to errors. To address the reliability problem, Polar Code is one coding method that can reach the channel capacity1. However, the 3D NAND flash memory channel is uncertain due to the variation of retention time and program/erase(P/E) cycle. So it is difficult to construct Polar Code in NAND flash memory. This paper proposes a new Polar Code construction method called Dynamic Merge Monte Carlo(DMMC). DMMC uses the Monte Carlo method to obtain the optimal Polar Code construction and then reduces the space overhead by combining similar construction so that it can be used in flash memory systems. Compared with the conventional method, the uncorrectable bit error rate(UBER) of the proposed method can reduce by up to 90.5%, and the read latency can reduce by more than 50%.

Reaping Both Latency and Reliability Benefits With Elaborate Sanitization Design for 3D TLC NAND Flash

With the rising security concern on modern storage systems, the concept of data sanitization has been widely investigated recently. Among the existing works targeting data sanitization, an overwriting-based approach, namely one-shot sanitization, is one of the most efficient sanitization approaches. Nonetheless, we find that the one-shot sanitization approach would fail to achieve precise data sanitization for 3D TLC NAND flash, because of incurring undesired data errors. That is, how to simultaneously realize precise sanitization and high security with decent latency and reliability on emerging storage devices remains unsolved. This work proposes an elaborate sanitization design that skillfully manipulates the threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$V_{t}$</tex-math></inline-formula> ) distribution of sanitized pages. Not only does the proposed design achieve precise sanitization and high security, but it also enhances read performance and data reliability. Specifically, this work elaborately sanitizes data by merging specific <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$V_{t}$</tex-math></inline-formula> distributions of the target physical page on 3D TLC NAND flash. Besides, the proposed approach further takes lateral charge migration into consideration to improve data reliability. We conduct a series of experiments to evaluate our proposed approach on real 3D TLC NAND flash. The experiment results demonstrate the proposed approach can achieve elaborate data sanitization under various scenarios and improve read performance by 29%.

LIAD: A Method for Extending the Effective Time of 3-D TLC NAND Flash Hard Decision

TLC NAND flash memory is widely used today due to its higher storage density and capacity. However, with the increase of the storage density, lower reliability results in more read times for flash memory and significantly reduces read performance. In order to avoid unnecessary read operations, this paper proposes a hard decision-soft decoding method called Location Information Assisted Decoding(LIAD) method, which determine the additional information required for decoding by mutual information, and then transmits the required information to correct the log-likelihood ratio(LLR). Different from the conventional LLR correction algorithm, this method does not require additional read operations and correct data. Only using sensing results, our method can reduce uncorrectable error bit rate(UBER) by up to 99%, and the system read latency under SSDsim1 simulation can be reduced by up to 53%.

A novel adaptive-refresh scheme to reduce refresh with page endurance variance in 3D TLC NAND flash memories

A novel adaptive-refresh scheme to reduce refresh with page endurance variance in 3D TLC NAND flash memories

Gradual Channel Estimation Method for TLC NAND Flash Memory

As the storage density of NAND flash increases, the reliability is significantly degraded, making NAND flash memory more sensitive to noise. Among all noise sources, retention noise is a major one. Error correction based on channel parameter estimation is an essential method to deal with retention noise. In this paper, a time-saving channel parameter estimation method for TLC NAND flash memory is proposed. Proposed method reduces estimation time by three improvements: (1) reducing fitted parameters in one iteration step, (2) using pre-derived values as initial guess values to decrease iteration steps, (3) utilizing parallelism between data sensing operations and computation. Compared with previous work, proposed method estimates parameters with higher accuracy and lower time overhead which is verified by experiment results.

System Performance Comparison of 3D Charge-Trap TLC NAND Flash and 2D Floating-Gate MLC NAND Flash Based SSDs

System Performance Comparison of 3D Charge-Trap TLC NAND Flash and 2D Floating-Gate MLC NAND Flash Based SSDs

Using Error Modes Aware LDPC to Improve Decoding Performance of 3-D TLC NAND Flash

3-D triple-level cell (3-D TLC) NAND flash has high storage density and capacity, but degrading data reliability due to high raw bit error rates induced by a certain number of program/erase cycles. To guarantee data reliability, low-density parity-check (LDPC) codes are selected as the error correction codes in modern flash memories because of strong error correction capability. However, directly adopting LDPC codes induces high decoding latency due to iterative updating of log-likelihood ratio (LLR) information in the decoding process. Increasing LLR information accuracy can greatly improve decoding performance. In this paper, we propose EMAL: using error modes aware LDPC codes for further enhancing the decoding performance of 3-D TLC NAND flash. We first obtain 3-D TLC error modes based on an FPGA testing platform, and then exploit the error modes to optimize LLR information and enable the decoding to converge at a high speed. The simulation results show that the decoding performance is significantly improved, resulting in reduced bit error rates and decoding latency.

Modeling of program Vth distribution for 3-D TLC NAND flash memory

This paper proposes a simulation method to model the program Vth distribution of 3-D vertical channel TLC/QLC charge-trapping NAND flash memory. The program Vth distribution can be calculated by considering ISPP noise, WL-WL interference, and the RTN effect of tunneling oxide and poly Si, which are the major physical factors affecting the width of program Vth distribution. Then, the program Vth distribution shapes with different ISPP incremental voltage steps are compared, and the results are found to be consistent with the experimental results. Code and layer-dependent coupling coefficients of WL-WL interference in 3-D vertical channel NAND flash memory are considered. The effect of RTN on the program Vth distribution is comprehensively studied. The program Vth distribution of a WL is calibrated with the measurement, and a good agreement is obtained, validating the array program Vth distribution simulation method. The simulation method can help in improving the reliability of 3-D TLC NAND flash memory and provides guidance for the design and optimization of 3-D QLC NAND flash memory technology.

Modeling the Endurance Reliability of Intradisk RAID Solutions for Mid-1X TLC NAND Flash Solid-State Drives

Ensuring data protection in solid state drives (SSDs) is vital in enterprise application scenario. However, as the reliability of their storage medium, namely, the NAND Flash, is decreasing at the same pace of the technology scaling, this activity is becoming nontrivial. The evaluation of different recovery strategies that employ complex error-correction codes and second-level error correction is becoming a de facto . In this paper, we model the endurance reliability of an advanced data protection methodology like the intradisk redundant array of independent disks (RAIDs) applied on mid-1X triple level cell NAND Flash-based SSD. The performed investigations include a parametric analysis of the uncorrectable bit-error rate. By developing a dedicated discrete-time Markov-chain model of an SSD, we evidenced that intradisk RAID5 and RAID6 allow achieving an inherent reliability level compliant with the qualification target for enterprise SSD. Finally, we provide a global picture of the disk economy when intradisk RAID is implemented.

Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives

NAND flash memory is ubiquitous in everyday life today because its capacity has continuously increased and cost has continuously decreased over decades. This positive growth is a result of two key trends: 1) effective process technology scaling; and 2) multi-level (e.g., MLC, TLC) cell data coding. Unfortunately, the reliability of raw data stored in flash memory has also continued to become more difficult to ensure, because these two trends lead to 1) fewer electrons in the flash memory cell floating gate to represent the data; and 2) larger cell-to-cell interference and disturbance effects. Without mitigation, worsening reliability can reduce the lifetime of NAND flash memory. As a result, flash memory controllers in solid-state drives (SSDs) have become much more sophisticated: they incorporate many effective techniques to ensure the correct interpretation of noisy data stored in flash memory cells. In this article, we review recent advances in SSD error characterization, mitigation, and data recovery techniques for reliability and lifetime improvement. We provide rigorous experimental data from state-of-the-art MLC and TLC NAND flash devices on various types of flash memory errors, to motivate the need for such techniques. Based on the understanding developed by the experimental characterization, we describe several mitigation and recovery techniques, including 1) cell-to-cell interference mitigation; 2) optimal multi-level cell sensing; 3) error correction using state-of-the-art algorithms and methods; and 4) data recovery when error correction fails. We quantify the reliability improvement provided by each of these techniques. Looking forward, we briefly discuss how flash memory and these techniques could evolve into the future.

MLC NAND Flash memory: Aging effect and chip/channel emulation

This work presents an FPGA-based emulator that can be used for emulating NAND Flash memories, either at the chip or at the channel level, along with the effect of aging on their performance. The emulator is based on a reconfigurable hardware-software architecture, which enables accurate representation of various NAND Flash technologies, focusing especially on MLC cases. The presented architecture can be used for emulating memories at the chip and channel level, while the proposed hardware platform can be used as a valuable tool for developing and evaluating memory-related algorithms and techniques. In this paper, we analyze the architecture of the NAND Flash memory emulator and we present details about its internal functionality. Using experimental results, we demonstrate the high accuracy achieved when it is used to emulate specific MLC and TLC NAND Flash chips and we describe how this custom hardware can be used to emulate a complete NAND Flash channel, which consists of multiple NAND Flash chips that share a common data path and support the execution of pipelined commands.

Hybrid triple-level-cell/multi-level-cell NAND flash storage array with chip exchangeable method

This paper proposes a mix-and-match design method for triple level cell (TLC)/multi level cell (MLC) NAND flash hybrid and exchangeable storage arrays. A TLC-NAND flash provides an low cost and high capacity memory solution. However the reliability and access latency of TLC NAND flash are degraded from MLC NAND flash. Additionally, the block unit write is preferable for TLC NAND flash since the write order is complicated due to narrow data margin and write disturbance. The proposed solution combines TLC and MLC NAND flash memories for a storage array. To reduce access to TLC NAND flash, the stored data is screened and only the static frozen data are stored into TLC NAND flash with a Round-Robin frozen data collection algorithm (RR-FDCA). Furthermore, the proposed chip exchanging method extends the solid-state drive (SSD) lifetime without system suspending. As a result, in spite of moderate characteristics of TLC NAND flash, the proposed storage array can achieve 29% write energy saving and 56% write performance enhancement with 17% cost reduction, compared with the conventional MLC-only SSD.

Bit-error rate improvement of TLC NAND Flash using state re-ordering

Bit-error rate improvement of TLC NAND Flash using state re-ordering