Generation Of Timing Signals Research Articles

A multi-functional arbitrary timing generator based on a digital-to-time converter.

This paper proposes a new high-resolution digital-to-time converter architecture based on a field programmable gate array and digital-to-analog converter (DAC). A real-time algorithm of time--amplitude mapping is proposed, which converts the vertical resolution of the DAC to the timing resolution and realizes the ultra-high resolution timing signal generation. Moreover, the relationship between the timing resolution and the vertical resolution and the sampling rate of DAC is discussed. Based on this, arbitrarily distributed random timing signals and editable timing signal sequence functions are realized. This method is verified in the experiment on Xilinx XCKU040 and Texas Instrument DAC37J82. Furthermore, a timing resolution of 1ps is realized. A time range of 4.2ns to 999s, an editable sequence length of 1-128k, and excellent nonlinear performance are achieved. In addition, functions for arbitrarily distributed random timing signals and signal bursts are tested. This method can be flexibly deployed on existing hardware and satisfy almost all test requirements.

Analysis and Design of the Control Sequence for an Ultrahigh Magnetic Field System

To meet the requirements of scientific research, a multi-coil ultrahigh magnetic field system (MUMS) has been developed at the Wuhan National Pulsed High Magnetic Field Centre (WHMFC) for generating a 100 T magnetic field. The MUMS is composed of outer, middle and inner coils with three pulsed power supplies, and the field waveforms generated by three coils are superimposed at the highest point to obtain an ultrahigh magnetic field. Due to the complex structure of the MUMS, to ensure reliable and efficient operation, first, the whole operation process of the MUMS is decomposed into a series of timing actions. On this basis, considering the constraint relationship between all timing actions, a general analysis and visual planning method based on the design structure matrix (DSM) and directed graph is proposed to design the control sequence, which can be directly described and executed sequentially in the control system. Moreover, to realize the design control sequence, the operation process of magnetic field systems is described by a state transition process in the state space, and a precise timing signal generator has been developed in the control system with a resolution of 5 ns. Finally, MUMS has been tested in experiments, and an 80 T magnetic field has been achieved. The results verify the validity of the designed control sequence, and the design method can be applied to various magnetic field systems.

Full-Circuit Implementation of Transformer Network Based on Memristor

As an emerging in-memory element, memristor has been widely used in various neural network circuits to represent the weights and accelerate the calculation. However, the Transformer Network (TN), one of the most important models for machine vision and natural language processing in recent years, has not yet been full-circuit implemented using memristors due to the complex calculation process and data storage. In order to carry out the computation of the TN more efficiently, this work proposes a memristor-based full-circuit implementation of the TN capable of: 1) a memristor crossbar module to preserve the weights of the TN and perform the vector-matrix multiplications; 2) an analog signal memory module to store the analog signal directly in near-memory mode; 3) function circuit modules to achieve five transformations, namely Softmax, Layer Normalization, ReLU, Multiply-add and Residual; 4) a timing signal generation module to schedule operations of the circuit. The proposed TN circuit can complete all calculations directly based on the analog signal without using any analog-digital converter (ADC), digital-analog converter (DAC) and digital memory. In addition, character image recognition experiments are carried out in PSPICE to verify the functional correctness of the designed circuit. The corresponding signal retention rates of the analog memory, the performance of the whole circuit, and the non-idealities of the memristors are also analyzed. The results indicate that the circuit has advantages in terms of area overhead, energy efficiency and anti-noise.

Rail-to-Rail Timing Signals Generation Using InGaZnO TFTs For Flexible X-Ray Detector

This paper reports on-chip rail-to-rail timing signals generation thin-film circuits for the first time. These circuits, based on a-IGZO thin-film transistors (TFTs) with a simple staggered bottom gate structure, allow row and column selection of a sensor matrix embedded in a flexible radiation sensing system. They include on-chip clock generator (ring oscillator), column selector (shift register) and row-selector (a frequency divider and a shift register). They are realised with rail-to-rail logic gates with level-shifting ability that can perform inversion and NAND logic operations. These logic gates are capable of providing full output swing between supply rails, V DD and V SS , by introducing a single additional switch for each input in bootstrapping logic gates. These circuits were characterised under normal ambient atmosphere and show an improved performance compared to the conventional logic gates with diode connected load and pseudo CMOS counterparts. By using these high-performance logic gates, a complete rail-to-rail frequency divider is presented from measurements using D-Flip Flop. In order to realize a complete compact system, an on-chip ring oscillator (output clock frequency around 1 kHz) and a shift register are also presented from simulations, where these circuits show a power consumption of 1.5 mW and 0.82 mW at a supply voltage of 8 V, respectively. While the circuit concepts described here were designed for an X-ray sensing system, they can be readily expanded to other domains where flexible on-chip timing signal generation is required, such as, smart packaging, biomedical wearable devices and RFIDs.

Low-Voltage High-Speed Ring Oscillator With a-InGaZnO TFTs

This paper presents a high-speed ring oscillator (RO) with amorphous Indium-Gallium-Zinc-Oxide Thin-film transistors (a-IGZO TFTs). The proposed RO reduces the delay of a single stage inverter using intermediate signals generated within the RO, hence, improving the speed. To validate the proposed idea, two conventional ROs (with diode-load load inverter and bootstrapped pseudo-CMOS inverter) and the proposed RO were fabricated at a temperature ≤ 180°C. Measured results of the proposed RO have shown a frequency and power-delay-product (PDP) of 173.2 kHz and 0.7 nJ at a supply voltage of 6V. Further, it shows approximately 155% (44%) increase in frequency and 14% (24.5%) decrease in PDP compared to diode-load inverter (bootstrapped pseudo-CMOS inverter) based ROs. Therefore, the proposed RO finds applications in low-voltage and high speed designs for timing signal generation.

Field Programmable Gate Array Based Control Signal Generator for Pulsed Radar

The objective of this paper is to present the architecture design and implementation of a software defined hardware module called Control Signal Generator (CSG) for pulsed RADAR (Radio Detection and Ranging) application. It is a digital, programmable, application-specific control timing signal generator for Disaster Management Synthetic Aperture Radar (DM-SAR)[1]. This module is a slave controller which receives command through asynchronous serial interface and generates programmable timings. Architecture evolved and the module is developed using Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL)[2] and successfully implemented on Xilinx Field Programmable Gate Array (FPGA) XCV600-6HQ240 [3].

Sharing Resources at Nonuniform Access Rates

We introduce DPPr (for ``Dining Philosophers Problem with rates'') as a generalization of the heavy-load case of the Dining Philosophers Problem (DPP). In DPPr, processes are required to be scheduled to access shared resources with prespecified relative frequencies. DPPr is an abstraction of resource-sharing problems to which the synchronization of some distributed algorithms for neural-network models and the generation of timing signals in asynchronous digital circuits are related. Two fully distributed, synchronous solutions are given for DPPr in this paper. The first solution employs a reduction to heavy-load DPP and after that a distributed scheduling mechanism that has been used to solve this problem with optimal concurrency. The second solution tackles the DPPr instance directly by operating on a multigraph based on that instance. We conclude by indicating how the two synchronous solutions carry over to the asynchronous case.

The use of associated particle timing based on the D + D reaction for elemental analysis of bulk samples such as the human body

The use of associated particle timing based on the D + D reaction has been demonstrated for elemental analysis of bulk samples such as the human body. The neutron energy of 2.8 MeV eliminates the background from organic matrices. The nanosecond timing of a HPGe detector renders it possible to identify the spatial origin of the measured γ radiation limiting the sensitive are to a single pixel. By this technique the background could be reduced by a factor of ≥ 1000, but the present set-up has achieved an effective factor only in the range 20–100, due to losses in the generation of timing signals. The very clean γ-spectra obtained permit the use of high efficiency scintillation detectors. Sensitivities for measuring Al, Ti, and Fe are presented at an extrapolated dose of 10 mSv.

Millisecond pulsar observation system using AOS

Communications Research Laboratory (CRL) developed a new millisecond pulsar observation system which used an Acousto-Optic Spectrometer (A0S). An AOS is simple and effective at dividing a wide band signal into many channels simultaneously. Using this system, we started preliminary observations of PSR1937+21 for the purpose of precise measurements of millisecond pulsar’s pulse timing.Fig. 1 shows a block diagram of our observation system using the 34m antenna of CRL. This antenna has several receivers (1.5, 2, 5, 8, 10, 15, 22, 43 GHz) with selective polarizer. We use 1.5GHz or 2GHz band for pulsar observations. An IF signal with 50MHz bandwidth is divided to 200kHz × 256ch by the AOS. The speed of data transporting rate from the camera is about 13μs which limits a time resolution. We get 100 bins per one period for PSR1937+21. The video averaging processor works as two 8bits A/D converters and an averager which allows 224pulses’ addition in each channel. The averaged data of each channel are combined after de-dispersion processing which is carried out in 1/1000 steps of the pulsar period. ¿From this final profile, the peak phase is defined as arrival pulse timing. Host#2 calculates thea prioripulse period by TEMPO program, and supplies it in real time to the synthesizer which controls the averaging trigger clock of the timing signal generator. The reference clock of this system is synchronized with UTC (CRL) via the GPS satellites. The difference between the reference clock and the internal clock of the timing signal generator is monitored using a time interval counter.

The Fermilab D0 master clock system

The clock system provides bunch-crossing-related timing signals to various detector subsystems. Accelerator synchronization and monitoring as well as timing signal generation and distribution are discussed. The system was built using three module types implemented in Eurostandard hardware with a VME communications interface. The first two types of modules were used to facilitate synchronization with the accelerator and to generate 23 timing signals that were programmable with one RF bucket (18.8-ns) resolution and 1-ns accuracy. Fifty-four modules of the third type were used to distribute the timing signals and two synchronous 53-MHz and 106-MHz clocks to various detector subsystems. >

Effect of synchronous activation of medullary inspiratory bulbo-spinal neurones on phrenic nerve discharge in cat.

The effects on phrenic nerve discharge elicited by intraspinal stimulation which produced synchronous activation of bulbo-spinal inspiratory neurones were investigated in chloralose-urethane anaesthetized, paralysed, vagotomized and artificially ventilated cats. Descending respiratory axons were activated in the ventrolateral spinal cord at the second cervical level using either monopolar or bipolar stimulation (25-200 microA, 100 microseconds, 1-300 Hz). Activation of bulbo-spinal axons was confirmed by recording both orthodromic phrenic nerve excitation and antidromic spike invasion of single, inspiratory modulated units in either the dorsal respiratory group (d.r.g.) or ventral respiratory group (v.r.g.). Antidromic activation of inspiratory bulbo-spinal neurones was confirmed by the criteria of high frequency following and collision tests. Spinal cord stimulation at intensities of 100 microA antidromically activated approximately half of the inspiratory bulbo-spinal neurones in the d.r.g. and v.r.g. Stimulation pulses delivered to the spinal cord elicited an orthodromic excitation of the ipsilateral phrenic nerve lasting 2-12 ms during inspiration. The onset latency of excitation was 2-4 ms, decreasing as inspiration progressed. Following the initial excitation there was a 4-30 ms period of reduced phrenic nerve discharge. Continuous trains of stimuli (less than 100 microA, 100 microseconds, 1-300 Hz) or phrenic gated trains delivered during every fourth inspiratory or expiratory cycle had little or no effect on the duration of inspiration or expiration. Brief trains (400 ms, 50 Hz, 100 microA) of bilateral spinal cord stimulation delivered at various delays from the onset of inspiration had only a transient effect on the pattern of phrenic nerve discharge, with no noticeable effect 60 ms after termination of stimulation. Based on the assumption that synchronous activation of a portion of the central pattern generator for respiration would phase shift or reset the rhythm, we conclude that the bulbo-spinal inspiratory neurones are not responsible for generation of respiratory timing signals and play, at most, a limited role in the generation of the augmenting central inspiratory activity.

10ps optoelectronic sampling system

Mode-locked laser pulses of less than 10 ps duration are used to switch electrical gates made from microstrip line on high-resistivity silicon, in 10 ps. These gates can generate steps and pulses of around 100 V with 10 ps rise and fall times. Sampling can also be accomplished with a 10 ps aperture. By combining a group of such gates, along with the generation of appropriate laser pulses and timing signals, a sampling system is formed. Simple time-domain reflectometry measurements are made to demonstrate the system and to show that practical transitions to these gates can be made for signals at least up to 35 GHz.

Erzeugung von Zeit-Referenzsignalen für das Neutronen-Flugzeitspektrometer am Hamburger Isochronzyklotron mittels Szintillatorfolien

The generation of timing signals by scintillation foils for the fast neutron time-of-flight spectrometer at the Hamburg Isochronous Cyclotron has been studied.

D2 Channel Bank: Digital Functions

This article describes the generation of timing signals and processing of digital information in the D2 Channel Bank. The transmitting portion of the D2 Channel Bank, which has four digital outputs, operates under the control of a single synchronous timing circuit. Because the four digital inputs to the receiving section of the D2 Bank are generally asynchronous, independent timing circuits are used for each of the four inputs. In addition, a separate clock is used in the receiver section to operate a single decoder shared by the four digital inputs. Digital processing of the transmitting terminal includes the serializing of the coder output, inserting of signaling and framing information, and converting the binary code into a bipolar format for transmission over the T1 digital line. To perform the inverse operation just mentioned, the receiving portion of the D2 Bank must extract timing information from the received digital signal and recover the framing information so that the decoded PCM words can be properly demultiplexed. In addition, queuing logic must be performed to permit sharing a single decoder among four asynchronous inputs.