Timing Recovery System Research Articles

Joint Batch Implementation of Blind Equalization and Timing Recovery

In conventional design of a digital receiver, the timing recovery system and the equalizer are considered separately. Actually, the two processes are coupled and interacted. The paper proposes a batch scheme for jointly performing blind equalization and timing recovery, that embeds the timing recovery process inside the batch blind equalization algorithm. The proposed scheme adds the timing offset of sampling and interpolation filter in the objective function of constant modulus algorithm, iteratively updates the timing offset and equalizer coefficients in batch approach, thus achieves equalization, symbol timing error detector and timing recovery jointly. In this way, the timing recovery and the equalization processes can be coordinated. Simulation results show the performance of equalization and timing recovery. 

An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects

A source synchronous I/O system based on high-density silicon carrier interconnects is introduced. Benefiting from the advantages of advanced silicon packaging technologies, the system uses 50 μm-pitch μC4s to reduce I/O cell size and fine-pitch interconnects on silicon carrier to achieve record-breaking interconnect density. An I/O architecture is introduced with link redundancy such that any link can be taken out of service for periodic recalibration without interrupting data transmission. A timing recovery system using two phase rotators shared across all bits in a receive bus is presented. To demonstrate these concepts, an I/O chipset using this architecture is fabricated in 45 nm SOI CMOS technology. It includes compact DFE-IIR equalization in the receiver, as well as a new all-CMOS phase rotator. The chipset is mounted to a silicon carrier tile via Pb-free SnAg μ C4 solder bumps. Chip-to-chip communication is achieved over ultra-dense interconnects with pitches of between 8 μm and 22 μm. 8 × 10-Gb/s data is received over distances up to 4 cm with a link energy efficiency of 5.3 pJ/bit from 1 V TX and RX power supplies. 8 × 9-Gb/s data is recovered from a 6-cm link with 16.3 dB loss at 4.5 GHz with an efficiency of 6.1 pJ/bit.

Read channel for signal waveform modulation multi-level disc

A novel read channel for signal waveform modulation multi-level disc is presented in this paper. This read channel employs timing recovery system and partial response maximum likelihood detector. Compared to the previous read channel composed of level detection and run-length detection, the present read channel shows superiority in capacity increase and robust performance. Especially, relying on the partial response maximum likelihood detection, lower bit error rate can be obtained.

Design of a Robust Multi-Channel Timing Recovery System With Imperfect Channel State Information for 10GBASE-T

The interdependence among multiple channels and the interaction between timing and equalization loops bring new challenges to the design of a multi-channel symbol timing recovery (STR) system for 10GBASE-T. In addition, the nonlinear Tomlinson-Harashima precoding (THP) technique used in the 10GBASE-T system is vulnerable to the imperfect channel state information (CSI). In this paper, we address the problem of timing inaccuracy caused by imperfect CSI and the problem of extracting correct timing information in the presence of channel-interdependence and loop-interaction for 10GBASE-T. This paper proposes a novel averaged-sampling-phase (ASP) hybrid STR scheme, which aligns the sampling clock phase of a single phase-locked loop (PLL) with an average value of the timing information provided by each wire pair so that the impact of the noisy timing information resulting from the imperfect CSI and the timing jitter of the single PLL is reduced. Moreover, a three-phase timing recovery strategy based on our architecture is also designed to correctly extract the timing information and effectively mitigate the loop-interaction. Simulation results demonstrate that the proposed multi-channel STR provides a complete loop-timed solution for 10GBASE-T and achieves a superior performance over conventional approaches in terms of robustness and timing jitter.

Read Channel for Multilevel Run-Length-Limited Read-Only Disc

A novel multilevel run-length-limited read channel which employs an interpolating timing recovery system and an adaptive partial-response maximum-likelihood (PRML) detector is developed. In proposed adaptive PRML detection system, we adopt a 112-levels adaptive Viterbi detector which uses every RF sample to adjust the reference levels for the calculation of branch metrics. The reference levels of adaptive Viterbi detector are also used to regenerate RF signals for phase error calculation. The usage of adaptive PRML detector makes the performance more robust, and the combination of Viterbi reference levels and RF generator makes the calculated phase errors more accurate.

Timing recovery in data storage systems: framework and approach of Kalman filtering

Recent error correction coding is able to work with low Signal-to-Noise Ratios (SNR), thus increasing the recording densities in data storage systems. With low SNR, conventional timing recovery is likely to lose stability and entire blocks of data may be lost. Reliable timing recovery is required in low SNR to reduce the loss of lock rate. In this paper, we introduce the framework of current timing recovery system, challenges of timing recovery in low SNR, and application of Kalman filtering to timing recovery. With Kalman filtering, timing recovery performance is improved in acquisition, tracking, and dropout compensation, and loss of lock rate is reduced.

Timing Recovery Method for Multilevel Run-Length-Limited Read-Only Disc

A novel timing recovery method for multilevel run-length-limited read-only disc is described. This timing recovery system employs interpolation method, which extracts multilevel run-length limited (ML-RLL) data directly from asynchronous oversampling RF data. The timing recovery system in the proposed read channel has a feedback architecture and consists entirely of digital circuits. It uses Viterbi detector output to calculate the phase error feedback to interpolator, and a special sync pattern is inserted to help frequency detection. The experimental results show that the acquisition time is much smaller than conventional timing recovery system.

Robust Read Channel System Directly Processing Asynchronous Sampling Data

In this study, we describe a robust read channel employing a novel timing recovery system and a unique Viterbi detector which extracts channel timing and channel data directly from asynchronous sampling data. The timing recovery system in the proposed read channel has feed-forward architecture and consists entirely of digital circuits. Thus, it enables robust timing recovery at high-speed and has no performance deterioration caused by variations in analog circuits. The Viterbi detector not only detects maximum-likelihood data using a reference level generator, but also transforms asynchronous data into pseudosynchronous data using two clocks, such as an asynchronous clock generated by a frequency synthesizer and a pseudosynchronous clock generated by a timing detector. The proposed read channel has achieved a constant and fast frequency acquisition time against initial frequency error and has improved its bit error rate performance. This robust read channel system can be used for high-speed signal processing and LSIs using nanometer-scale semiconductor processes.

Efficient implementation of polynomial interpolation filters for full digital receivers

Interpolation filters are widely used in symbol timing recovery systems to interpolate new sample values at arbitrary points between the existing discrete-time samples. This paper presents an efficient way to implement polynomial interpolation filters based on the analysis of constraints which are used for optimization. The proposed technique does not require two sub-filters in the well-known Farrow structure, which leads to a very efficient interpolator. Implementation examples are included illustrating the efficiency of the proposed method.

Development of Signal Interpolated Phase Timing Recovery System for High Density Magneto-Optical Disks

We developed a new timing recovery system for magneto-optical disks (MO) with a higher recording density and higher transfer rate but it is difficult to achieve these without signal to noise ratio (SNR) degradation in the MO readout signal. Therefore, for signal processing, we have developed a turbo code technology, [rf1] which can obtain a high enough coding gain. However, as optimal phase to obtain the optimum performance of the turbo code must be detected, we developed a very precise phase timing recovery system that works under a degraded SNR in the MO readout signal. Moreover, as the turbo code is a kind of block code, which requires decoding by a turbo block unit, we also developed a system for detecting the start point for turbo decoding. We developed a new timing recovery system and, in this paper, we report architecture and performance evaluations of this system.

A signal interpolated timing recovery system with frequency offset detector

A method of frequency offset detection for signal interpolated timing recovery is proposed. The frequency offset is estimated by measuring the correlation between the preamble and the reference sinusoid. When the frequency offset exists, the phase error changes linearly. The offset can be estimated by the gradient of the phase errors. The simulation results show that the method significantly improves the stability of the timing recovery and increases the capture range. It also decreases the preamble length and results in higher format efficiency.

Timing acquisition for low-SNR data storage channels

As magnetic data storage densities are pushed toward Tb/in/sup 2/ and beyond, advanced signal-detection algorithms are being suggested to cope with the expected lower signal-to-noise ratios (SNRs). However, at low SNR, loss of lock will frequently occur in the current timing-recovery system. This paper illustrates that inadequate timing acquisition is the major cause for loss of lock in hard disk drives. Motivated by the digital zero phase start (DZPS) technique, a digital zero frequency/phase start (DZF/PS) technique is proposed to quickly reduce the initial frequency and phase errors. Kalman filter-based acquisition can be used subsequently to fine-tune acquisition based on the buffered symbol-rate samples of a preamble readout signal. Numerical simulations show that DZF/PS can reduce preamble length significantly (when used in acquisition) compared with DZPS.

A study of timing recovery for perpendicular magnetic recording

Performance of a timing recovery system for perpendicular magnetic recording channels is studied. The system detects timing error from pre-equalized waveform of a basic PR system such as PR1, and corrects the timing of sampled sequence using an interpolated filter. The results show that the system which uses PR1 system as the pre-equalization and directly compensates the reproduced waveform exhibits good performance.

All digital timing recovery and programmable gain amplifier controller for VDSL transmission

We discuss all digital timing recovery and programmable gain amplifier (PGA) controller for carrierless amplitude and phase (CAP) modulation based very high-rate digital subscriber line (VDSL) system. We first investigate statistical properties of timing jitter of symbol timing recovery circuit for VDSL application. Analytical expressions of the timing jitter for an envelope-based timing recovery system, such as squarer-based timing recovery (S-TR) and absolute-value-based timing recovery (A-TR) schemes, are derived in the presence of additive white Gaussian noise (AWGN) or far-end crosstalk (FEXT). In particular, the analytical and simulation results of the timing jitter performance are presented and compared for a 51.84 Mb/s 16-CAP VDSL system. The A-TR system implemented digitally meets the DAVIC's VDSL system requirement, which specifies the maximum peak-to-peak jitter value of 1.5 nsec and the acquisition time of 20 msec. We also present simulation results for PGA controller and blind equalization, which have been incorporated to implement CAP-based VDSL transmission system.

An in-service measurement system for the quality analysis of facsimile transmissions

The paper presents a measurement technique for the assessment of the degree of quality of facsimile transmissions over a telephone-type network that can be performed while the communication lines are in use. The main impairments introduced by the telecommunication channel are continuously measured by using a blind equalization technique and a timing recovery system, thus assuring a high accuracy with a reasonable measurement time, even under poor signal-to-noise ratio (SNR) conditions. Experimental results, that confirm the good performance of the proposed method, are reported and discussed.

Presence of residual echo and impulsive noise

A general analysis is presented for the jitter performance of a common type of symbol timing recovery (STR) system employed in a digital subscriber loop (DSL) transceiver for high-speed digital data transmission over twisted copper pair cables in the presence of residual echo and impulsive noise (IN). Numerical results, obtained for an experimental study of a timing recovery system, show that the presence of these disturbing signals can substantially degrade the STR performance.

Correction to "A New Approach for Evaluating the Performance of a Symbol Timing Recovery System Empl

Correction to "A New Approach for Evaluating the Performance of a Symbol Timing Recovery System Empl

A new approach for evaluating the performance of a symbol timing recovery system employing a general type of nonlinearity

A new technique is presented for evaluating the jitter performance of a symbol timing recovery (STR) subsystem for digital data transmission systems. The STR system consists of any even-symmetric zero-memory nonlinear device followed by a narrowband filter tuned to the pulse repetition frequency. Exact analytical expressions are derived for the mean and the mean-square values of the timing wave, based on iterative computations of high-order moments of the input signal. Then, the root mean-square (RMS) jitter performance is determined as a function of various system parameters such as the power series expansion of the zero-memory nonlinear device, the rolloff factor of the input pulse shape, and the postfiltering. Finally, the numerical results obtained from some specific examples serve to illustrate several aspects of the timing recovery problem.

Adaptive nonlinear decision feedback equalization with channel estimation and timing recovery in digital magnetic recording systems

In high density digital magnetic recording systems, the nonlinear effects in the write process appear in the readback waveform as shifts in the peak positions and changes in the amplitude. The pulse shift causes a nonlinear intersymbol interference (ISI) on the readback signal. In this paper, a Volterra-DFE, in which a Volterra filter is used in the feedback section of decision feedback structure, is proposed to equalize the nonlinear ISI. By theoretical analysis, the minimum mean squared error (MSE) of the Volterra-DFE is found to be a function of sampling phase. This will affect the output signal-to-noise ratio (SNR) of the playback system. A baud-rate timing recovery system in conjunction with a channel estimator is used to operate the sampling clock on the optimum phase. By computer simulation, Volterra-DFE is found to outperform conventional DFE in both output SNR and BER in a high density magnetic recording system.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Symbol timing recovery in digital subscribers loops in the presence of residual echo and crosstalk

A general analysis is presented for the jitter performance of a common symbol timing recovery (STR) system used in a digital subscriber loop (DSL) transceiver that uses adaptive echo cancellation for high-speed digital communications. Exact analytical expressions for the mean and variance of the timing wave and for the RMS phase jitter are derived as a function of the bandwidth of the postfilter for a given set of input parameters representing a particular digital subscriber loop and its noise environment, including such effects as residual echo and crosstalk. Numerical results show that the presence of these disturbing signals can substantially degrade the STR performance. The effect of the excess bandwidth factor of the prefilter on this degradation is investigated. >