In this paper, we present a timing-driven placement algorithm for standard cell layout, and propose a path-based timing-driven placement algorithm. To estimate the accurate interconnection delay, the proposed algorithm adopts the Elmore delay model [8] so that we can apply the proposed algorithm to wider technologies than the conventional algorithms. The proposed algorithm is based on hierarchical partitioning and nonlinear programming, and consists of three phases. In the first phase, the algorithm produces an initial placement by a timing-driven min-cut partitioning algorithm. Next, an iterative improvement phase improves the initial placement by nonlinear programming. The improvement problem is formulated as the problem of minimizing the total wire length subject to timing constraints. Finally, a row assignment phase considering timing constraint arranges cells in rows. From the experimental results comparing with RITUAL [29], the proposed algorithm is much better than RITUAL in regard to the maximum violation ratio, the total wire length, and the cut size, and is more effective in point of the interconnection delay model and its extendability.