Timing Analysis Attacks Research Articles

A Defense Mechanism Against Timing Attacks on User Privacy in ICN

While in-network caching is an essential feature of Information Centric Networks (ICN) for improved content dissemination and reducing the bandwidth consumption at the core of the network, it is prone to many privacy threats. For example, an adversary can passively breach the privacy of a consumer by simply analyzing the different retrieval times for the same content. This paper aims to address this problem of timing analysis attacks by developing privacy-enhancing caching strategies. The proposed caching strategies use two privacy metrics, namely mutual information from information theory and differential privacy, and formulates a privacy enhancing distributed optimization problem with the objective of optimizing the network cost incurred. We efficiently solve the optimization problem by considering it as a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$n$ </tex-math></inline-formula> -player, non-cooperative game. We show that Nash equilibrium exists for this game and compute it using an iterative best response algorithm. We compare and validate the performance of our approach on realistic network topologies by comparing it with the existing approaches in literature and the global optimal solutions.

Design and Validation of Low-Power Secure and Dependable Elliptic Curve Cryptosystem

The elliptic curve cryptosystem (ECC) has been proven to be vulnerable to non-invasive side-channel analysis attacks, such as timing, power, visible light, electromagnetic emanation, and acoustic analysis attacks. In ECC, the scalar multiplication component is considered to be highly susceptible to side-channel attacks (SCAs) because it consumes the most power and leaks the most information. In this work, we design a robust asynchronous circuit for scalar multiplication that is resistant to state-of-the-art timing, power, and fault analysis attacks. We leverage the genetic algorithm with multi-objective fitness function to generate a standard Boolean logic-based combinational circuit for scalar multiplication. We transform this circuit into a multi-threshold dual-spacer dual-rail delay-insensitive logic (MTD3L) circuit. We then design point-addition and point-doubling circuits using the same procedure. Finally, we integrate these components together into a complete secure and dependable ECC processor. We design and validate the ECC processor using Xilinx ISE 14.7 and implement it in a Xilinx Kintex-7 field-programmable gate array (FPGA).

A Resource-Efficient and Side-Channel Secure Hardware Implementation of Ring-LWE Cryptographic Processor

Lattice-based cryptography has shown great potential due to its resistance against quantum attacks. With the security requirements for high-precision Gaussian sampling and complex polynomial multiplication over rings, as well as storage of large public-keys, it is extremely challengeable but important to implement lattice-based schemes on resources constrained devices. In this paper, a resource-efficient and side-channel secure Ring-LWE cryptographic processor is presented. A discrete Gaussian sampler with constant response time, high precision, and large distribution tails is designed. The proposed Gaussian sampler is proven to be secure against side-channel timing attack according to the timing analysis attack results on a FPGA-based testing platform. A universal module MPE (Modular Processing Element) is designed to carry out all basic modular operations for Ring-LWE cryptography with high speed. The prototype verification is performed on the Xilinx Spartan-6 FPGA platform. The processor can execute an encryption/decryption operation on a 256-bit message in 4.5/0.9 ms whilst it consumes only 1307 LUTs, 889 FFs, 4 BRAMs, and none DSP module. Compared with other related hardware implementations, the Ring-LWE processor is advantageous not only in hardware efficiency but also in secure protection against side-channel attacks.

Information Processing and Security Analysis of Shared System Resource Based Architectures

Background: Nowadays, service-oriented architectures and cloud-based infrastructures are widely used in manufacturing industries and IT organizations. These architectures and infrastructures are based on shared system resources. In some organizations, system resources like a printer, photocopy machines, and scanners are also shared among the members of the organization. The purpose of the proposed work is to model various types of shared system resources, shared system resources based architecture/infrastructure and analyze the model to identify the possible security risk associated with shared system resources and shared system resources based architecture/infrastructure. Design Approach: To model shared system resources and shared system resources based architecture/Infrastructure, Petri net and its variations are used. For security analysis of the Petri net based model of the shared system resource, Petri net algebra based concepts are applied. Results: The present paper successfully demonstrates that the proposed Petri net based modeling approach can be used for quantitative and qualitative security analysis of shared system resources and shared system resources based architecture/infrastructure. For quantitative analysis of security risk associated with shared system resources, information theoretic concepts are used. To demonstrate the effectiveness of the proposed method, case studies are also incorporated in the present paper. The proposed approach can take various security risk factors like timing analysis attack, information leakage due to confidentiality policy violation and power analysis attack into the consideration while analyzing the security of shared system resources in the industrial environment.

FPGA Based High Speed SPA Resistant Elliptic Curve Scalar Multiplier Architecture

The higher computational complexity of an elliptic curve scalar point multiplication operation limits its implementation on general purpose processors. Dedicated hardware architectures are essential to reduce the computational time, which results in a substantial increase in the performance of associated cryptographic protocols. This paper presents a unified architecture to compute modular addition, subtraction, and multiplication operations over a finite field of large prime characteristicGF(p). Subsequently, dual instances of the unified architecture are utilized in the design of high speed elliptic curve scalar multiplier architecture. The proposed architecture is synthesized and implemented on several different Xilinx FPGA platforms for different field sizes. The proposed design computes a 192-bit elliptic curve scalar multiplication in 2.3 ms on Virtex-4 FPGA platform. It is 34%faster and requires 40%fewer clock cycles for elliptic curve scalar multiplication and consumes considerable fewer FPGA slices as compared to the other existing designs. The proposed design is also resistant to the timing and simple power analysis (SPA) attacks; therefore it is a good choice in the construction of fast and secure elliptic curve based cryptographic protocols.

Security against Timing Analysis Attack

Timing attack is the type of side-channel attack involves the time taken to complete critical operations. Securing crypto processor from timing attack is critical issue. This paper implements the Bernstein’s Timing Attack and timing attack based on hamming weight. The countermeasures of Bernstein’s Timing attack are implemented in our experimental test bed and their performance is compared. This paper also proposes the key recovery method based on timing attack using hamming weight of the key.

PROARTIS

Static timing analysis is the state-of-the-art practice of ascertaining the timing behavior of current-generation real-time embedded systems. The adoption of more complex hardware to respond to the increasing demand for computing power in next-generation systems exacerbates some of the limitations of static timing analysis. In particular, the effort of acquiring (1) detailed information on the hardware to develop an accurate model of its execution latency as well as (2) knowledge of the timing behavior of the program in the presence of varying hardware conditions, such as those dependent on the history of previously executed instructions. We call these problems the timing analysis walls. In this vision-statement article, we present probabilistic timing analysis , a novel approach to the analysis of the timing behavior of next-generation real-time embedded systems. We show how probabilistic timing analysis attacks the timing analysis walls; we then illustrate the mathematical foundations on which this method is based and the challenges we face in the effort of efficiently implementing it. We also present experimental evidence that shows how probabilistic timing analysis reduces the extent of knowledge about the execution platform required to produce probabilistically accurate WCET estimations.

Mitigating power- and timing-based side-channel attacks using dual-spacer dual-rail delay-insensitive asynchronous logic

Side-channel attacks have become a prevalent research topic for electronic circuits in security-related applications, due to the strong correlation between data pattern and circuit external characteristics which can be easily measured. By monitoring the power/timing information of a synchronous circuit, an attacker can easily obtain the secret data stored on the device. Although dual-rail asynchronous circuits have more stable power traces, they are still vulnerable to power-based attacks because of the imbalanced loads between the two rails of each signal. Moreover, asynchronous circuits are among the most prone to timing attacks since their delays are strongly data dependent.Dual-spacer dual-rail delay-insensitive Logic (D3L), presented in this paper, is able to mitigate both power- and timing-based side-channel attacks. In a D3L circuit, power consumption is decoupled from data pattern by using a dual-spacer protocol which guarantees balanced switching activities between the two rails of each signal, while timing-data correlation is broken by inserting random delays. Three Advanced Encryption Standard cores have been designed using synchronous logic, traditional dual-rail asynchronous logic, and D3L. Correlation Power Analysis and Timing Analysis attacks were applied and the results show that the D3L design is able to render both attacks unsuccessful, while the other two circuits have vulnerabilities.