Time Walk Compensation Research Articles

Development of a shaper and discriminator chip with time walk compensation for HFRS-TPC detector

In this paper, a shaper and discriminator ASIC chip with time-walk compensation(TWC) is designed using 180 nm CMOS technology for a TPC detector which will be assembled on High energy FRagment Separator(HFRS) beamlines under construction. It comprises a fast CR-RC shaper, two comparators, and a TWC module. The peak time of the shaper is 30 ns, and the propagation delay of the comparator is 2.4 ns (25 mV Overdrive). When the dynamic range of the TPC output charge is from 10 fC to 1000 fC, the time error of the trigger signal produced by the ASIC was measured to be less than 2 ns.

Improving the timing accuracy of SiPMs by time‐walk compensation

Timing measurements with silicon photomultipliers (SiPMs) are affected by the major issue of the so-called time-walk effect; this is due to the intrinsic architecture of SiPM devices. A new technique for time-walk compensation in timing measurements with SiPMs is presented and discussed, feasible with a low-complexity and low-cost circuitry and able to improve the timing accuracy. The validity of the presented technique has been experimentally proven with a 3 × 3 mm2 Hamamatsu MPPC, achieving a jitter reduction of a factor 2.85 compared with the case without time-walk compensation. To perform the experimental validation, a discrete-components transimpedance amplifier is developed with large bandwidth and low jitter, specifically designed to read-out and amplify the SiPM signal.

High-voltage CMOS detectors

High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. HVCMOS sensors will be used in Mu3e experiment at PSI and are considered as an option for both ATLAS and CLIC (CERN). Radiation tolerance and time walk compensation have been tested and results are presented.

A 130nm ASIC prototype for the NA62 Gigatracker readout

Abstract One of the most challenging detectors of the NA62 experiment is the silicon tracker, called Gigatracker. It consists of three hybrid silicon pixel stations, each one covering an area of 27 mm×60 mm. While the maximum pixel size is fairly large, 300 μ m × 300 μ m the system has to sustain a very high particle rate, 1.5 MHz/mm 2 , which corresponds to 800 MHz for each station. To obtain an efficient tracking with such a high rate the required track timing resolution is 150 ps (rms). Therefore the front-end ASIC should provide for each pixel a 200 ps time measurement capability, thus leading to the requirement of time walk compensation and very compact TDCs. Moreover, Single Event Upset protection has to be implemented in order to protect the digital circuitry. An ASIC prototype has been realized in CMOS 130 nm technology, containing three pixel columns. The chip performs the time walk compensation by a Constant Fraction Discriminator circuit, while the time measurement is performed by a Time to Amplitude Converter based TDC, both of them implemented on each pixel cell. The End of Column circuit containing only digital logic is responsible for the data readout from the pixel cell. The whole chip works with a system clock of 160 MHz and the digital logic is SEU protected by the use of Hamming codes. The detailed architecture of the ASIC prototype and test results are presented.

Photon number resolving in geiger mode avalanche photodiode photon counters

The paper reports on research and development in the field of avalanche photodiodes operated as photon counters in a Geiger mode. A technique has been developed and tested that permits estimation of the photon number involved in a detection process. It can be applied in a time correlated photon counting experiment simultaneously with original required time interval estimation. A time walk compensation circuit provides uniform electrical pulses, and the time interval between them is related to the number of photons detected. Employing a picosecond event timing device, the photon number can be estimated within the dynamic range 1–1000 photons with resolution better than a factor of three.

A CMOS time-of-flight system-on-a-chip for spacecraft instruments

A CMOS time-of-flight (TOF) system-on-a-chip (SoC) for precise time-interval measurement with low power and high rate has been developed. Microchannel plate electron multipliers or photomultiplier tubes (PMTs) typically produce the start-stop delta-Ts of radiation events to be processed. The TOF chip includes two constant fraction discriminators (CFDs) and a time-to-digital converter (TDC). The CFDs interface to start and stop anodes through two simple preamplifiers and perform the signal processing for time walk compensation. The TDC digitizes the time difference with reference to an off-chip precise oscillator. The design is full custom in both the analog and the digital sections. A first version of the TOF chip developed in a 0.8-/spl mu/m CMOS process achieved CFD time walk of /spl sim/350 ps for an input amplitude dynamic range of 40 dB and a combined CFD+TDC time jitter of /spl sim/180 ps. The total power dissipation was /spl sim/20 mW at an event rate of 100 K/s and /spl sim/30 mW at a rate of 1 Meg/s. This chip is part of the high-energy neutral atom instrument onboard the NASA/IMAGE spacecraft launched in March 2000. It is selected for many other instruments, including the particle sensor, the fast plasma sensor, and the laser altimeter of Messenger for the Mercury exploration to be launched in 2004.

A CMOS multichannel IC for pulse timing measurements with 1-mV sensitivity

A multichannel data acquisition circuit that measures the occurrence times of input pulses relative to a 62.5-MHz clock has been integrated in a 1.2-/spl mu/m CMOS technology. The pulse timing measurement channels are sensitive to input pulses with peak amplitudes as small as 1 mV. Each channel consists of a wideband preamplifier, a tail-cancellation filter, a timing discriminator with time-walk compensation, and a time digitizer. A phase-locked loop (PLL) reference for the time digitizer is included in the circuit. An overall channel timing error of 0.46 ns RMS has been achieved, with negligible channel-to-channel crosstalk, at a power dissipation of 50 mW/channel.

An analog front-end bipolar-transistor integrated circuit for the SDC silicon tracker

A low-noise, low-power, high-bandwidth, radiation hard, silicon bipolar-transistor full-custom integrated circuit (IC) containing 64 channels of analog signal processing has been developed for the SDC silicon tracker The IC was designed and tested at LBL and was fabricated using AT&T's CBIC-U2, 4 GHz f/sub /spl tau// complementary bipolar technology. Each channel contains the following functions: low-noise preamplification, pulse shaping and threshold discrimination. This is the first iteration of the production analog IC for the SDC silicon tracker. The IC is laid out to directly match the 50 /spl mu/m pitch double-sided silicon strip detector. The chip measures 6.8 mm/spl times/3.1 mm and contains 3,600 transistors. Three stages of amplification provide 180 mV/fC of gain with a 35 nsec peaking time at the comparator input. For a 14 pF detector capacitance, the equivalent noise charge is 1300 el. RMS at a power consumption of 1 mW/channel from a single 3.5 V supply. With the discriminator threshold set to 4 times the noise level, a 16 nsec time-walk for 1.25 to 10 fC signals is achieved using a time-walk compensation network. Irradiation tests at TRIUMF to a /spl Phi/=10/sup 14/ protons/cm/sup 2/ have been performed on the IC, demonstrating the radiation hardness of the complementary bipolar process. >