Time Stamp Counter Research Articles

TS-Perf: General Performance Measurement of Trusted Execution Environment and Rich Execution Environment on Intel SGX, Arm TrustZone, and RISC-V Keystone

A trusted execution environment (TEE) is a new hardware security feature that is isolated from a normal OS (i.e., rich execution environment (REE)). The TEE enables us to run a critical process, but the behavior is invisible from the normal OS, which makes it difficult to debug and tune the performance. In addition, the hardware/software architectures of TEE are different on CPUs. For example, Intel SGX allows user-mode only, although Arm TrustZone and RISC-V Keystone run a trusted OS. In addition, each TEE has each SDK for programming. Each SDK offers own APIs and makes difficult to write a common program. These features make it difficult to compare the performance fairly between TEE and REE on different CPUs. To obtain precise performance and behavior in TEE, we propose TS-perf which is a compiler-based performance measurement method. TS-perf accesses the hardware timestamp counter in TEE as well as REE and keeps a precise log. The codes for measurement are inserted in a TEE binary by the compiler options (i.e., profile option, constructor, and destructor). Furthermore, we utilize the separate compilation technique, and the same benchmark binary is used for a fair comparison between TEE and REE. The architecture of TS-perf is general and implemented for three TEE architectures (Arm TrustZone, Intel SGX, and RISC-V Keystone). TS-perf measures the performance of GlobalPlatform’s TEE internal APIs, matrix multiplication, memory access, and storage access. The comparisons show the difference in performance between TEE and REE and the unusual behavior of trusted applications (TAs).

Precise relative clock synchronization for distributed control using TSC registers

Precise clock synchronization is essential in emerging time-critical distributed control systems operating over computer networks where the clock synchronization requirements are mostly focused on relative clock synchronization and high synchronization precision. Existing clock synchronization techniques such as the Network Time Protocol (NTP) and the IEEE 1588 standard can be difficult to apply to such systems because of the highly precise hardware clocks required, due to network congestion caused by a high frequency of synchronization message transmissions, and high overheads. In response, we present a Time Stamp Counter based precise Relative Clock Synchronization Protocol (TSC-RCSP) for distributed control applications operating over local-area networks (LANs). In our protocol a software clock based on the TSC register, counting CPU cycles, is adopted in the time clients and server. TSC-based clocks offer clients a precise, stable and low-cost clock synchronization solution. Experimental results show that clock precision in the order of 10 microseconds can be achieved in small-scale LAN systems. Such clock precision is much higher than that of a processor׳s Time-Of-Day clock and is easily sufficient for most distributed real-time control applications over LANs.

A New Approach of Time-Synchronization for LAN Based on General PC

Possessing a shrewd accurate time synchronous mechanism is the prerequisite of many network applications. This paper puts forward a kind of time synchronous method for LAN(local area network) based on general PC, replaces systematic clock with TSC(time stamp counter) register as synchronous time source, achieves synchronization through a client and server style, it is easy to calculate and needs less expense. The result of experiment shows that the synchronous precision of this method is higher, and can be kept longer; it also shows that this method is suitable for the application occasion which requires higher time-synchronization.

Platform Independent Timing of Java Virtual Machine Bytecode Instructions

The accurate measurement of the execution time of Java bytecode is one factor that is important in order to estimate the total execution time of a Java application running on a Java Virtual Machine. In this paper we document the difficulties and solutions for the accurate timing of Java bytecode. We also identify trends across the execution times recorded for all imperative Java bytecodes. These trends would suggest that knowing the execution times of a small subset of the Java bytecode instructions would be sufficient to model the execution times of the remainder. We first review a statistical approach for achieving high precision timing results for Java bytecode using low precision timers and then present a more suitable technique using homogeneous bytecode sequences for recording such information. We finally compare instruction execution times acquired using this platform independent technique against execution times recorded using the read time stamp counter assembly instruction. In particular our results show the existence of a strong linear correlation between both techniques.

A High Precision Approach of Network Delay Measurement Based on General PC

Delay is the foundation for accurately measuring network performance metrics such as delay jitter, bandwidth, etc. While the delay measurement methods currently used have poor precision, for there exist clock errors and location errors. In this paper, an improved method for delay measurement is proposed. It replaces system clock with TSC (time stamp counter) register as time-stamping to eliminate clock errors, and it removes the time-stamping place from application to network driver to eliminate location errors. The precision has been elevated largely. Experiments show that when comparing with traditional methods under different packet lengths, the improved method can reduce measurement errors 21%~150%, and the measured delays are more stable. Furthermore, it basically has no effect on system throughput. The improved measurement method is based on general PC, so it has lower measurement cost and can be applied widely.

Dynamic Estimation of Task Level Parallelism with Operating System Support

The amount of Task Level Parallelism (TLP) in runtime workload is useful information to determine the efficient usage of multiprocessors. This paper presents mechanisms to dynamically estimate the amount of TLP in runtime workloads. Modifications are added to the operating system (OS) to collect information about processor utilization, task activities, from which TLP can be calculated. By effectively utilizing the Time Stamp Counter (TSC) hardware, the task activities can be monitored at fine time resolution, resulting in capability of estimation of TLP at fine granularity. We implement the mechanisms on a recent version of Linux OS. Evaluation results indicate that the mechanisms can estimate TLP accurately for various kinds of workloads with small overheads.

A HIGH-PRECISION, LOW COST SYSTEM FOR EVALUATING FINGER-TAPPING TASKS

Finger-tapping test is extensively employed to assess motor asymmetry in brain damaged patients and also to study the relationship between handedness and performance in normal subjects. The aim of this study was to develop a computer based finger-tapping system that could provide quantitative measures of finger-tapping performance. The system is designed to be used in a standard personel computer without the need of any other hardware. The software is written in Borland Delphi® 6.0 for Microsoft® Windows 98® and higher operating systems. Beginning with the Pentium® processor, it could be possible to access a time-stamp counter. The time-stamp counter is a 64-bit machine specific register that is incremented by every clock cycle, and keeps an accurate count of every cycle that occurs on the processor. By using a computer with 1 GHz processor speed it is possible to reach a high precision time resolution of 1 μs in finger-tapping tests. Our future prospects for the system are to improve it with various tools such as synchronized recording of electromyography, tapping force monitoring, monitoring of finger angle, and the response to different stimulus parameters by adding appropriate hardware and procedure.

Enhancing time-stamp counter phase modulation measurements

This paper demonstrates that digital signal processing techniques can enhance the quality of phase modulation measurements produced by a time-stamp (phase digitizing) frequency counter. A typical time-stamp counter utilizes a digital divider to reduce signal frequency to the desired sample rate. Unfortunately, division also reduces phase modulation to the point where useful information may be obscured by counter measurement uncertainty (jitter). An analogy between an analog-to-digital converter (ADC) and a time-stamp counter predicts that the counter induced modulation can be modeled as random noise which is white in phase. The noise magnitude is directly related to the instrument's resolution specification. Fourier analysis, subject to some restrictions, can compute the power spectra of phase or frequency modulation, revealing even low level responses. A number of techniques can be used to reduce the amount of counter induced noise that appears on time domain plots of phase and frequency modulation. Experimental data, generated by a prototype counter, illustrates the type of results that can be expected from Fourier analysis and various noise reduction techniques.