Time-slot Interchange Research Articles

Intelligent Resource Management Using Multiagent Double Deep Q-Networks to Guarantee Strict Reliability and Low Latency in IoT Network

With the rapid adoption of the Internet of Things, it is necessary to go beyond fifth-generation applications and apply stringent high reliability and low latency requirements, closely related to strict delay demands. These requirements support massive network connectivity for multiple Internet of Things devices. Hence, in this paper, we optimize energy efficiency and achieve quality-of-service requirements by mitigating co-channel interference, performing efficient power control of transmitters, and harvesting energy using time-slot exchanges. Due to a nonconvex optimization problem, we propose an iterative algorithm for power allocation and time slot interchange to reduce the computational complexity. To achieve a high degree of ultra-reliability and low latency with quality-of-service-aware instantaneous reward under massive connectivity, we efficiently employ multiagent reinforcement learning by addressing the intelligent resource management problem via a novel Double Deep Q Network. The network prioritizes experience replay to exploit the best policy and maximize accumulative rewards. It also learns the optimal policy and enhances learning efficiency by maximizing its reward function to make decisions with high intelligence and guarantee strict ultra-reliability and low latency. The simulation result shows that the Double Deep Q Network with prioritized experience replay can guarantee stringent ultra-reliability and low latency. As a result, the co-channel interference between transmission links and the high-power consumption density associated with the massive connectivity of the Internet of Things devices are mitigated.

Silicon Photonics towards Disaggregation of Resources in Data Centers

In this paper, we demonstrate two subsystems based on Silicon Photonics, towards meeting the network requirements imposed by disaggregation of resources in Data Centers. The first one utilizes a 4 × 4 Silicon photonics switching matrix, employing Mach Zehnder Interferometers (MZIs) with Electro-Optical phase shifters, directly controlled by a high speed Field Programmable Gate Array (FPGA) board for the successful implementation of a Bloom-Filter (BF)-label forwarding scheme. The FPGA is responsible for extracting the BF-label from the incoming optical packets, carrying out the BF-based forwarding function, determining the appropriate switching state and generating the corresponding control signals towards conveying incoming packets to the desired output port of the matrix. The BF-label based packet forwarding scheme allows rapid reconfiguration of the optical switch, while at the same time reduces the memory requirements of the node’s lookup table. Successful operation for 10 Gb/s data packets is reported for a 1 × 4 routing layout. The second subsystem utilizes three integrated spiral waveguides, with record-high 2.6 ns/mm2, delay versus footprint efficiency, along with two Semiconductor Optical Amplifier Mach-Zehnder Interferometer (SOA-MZI) wavelength converters, to construct a variable optical buffer and a Time Slot Interchange module. Error-free on-chip variable delay buffering from 6.5 ns up to 17.2 ns and successful timeslot interchanging for 10 Gb/s optical packets are presented.

Reconfigurable Time Slot Interchange Based on Four-Wave Mixing and a Programmable Planar Lightwave Circuit

We demonstrate the all-optical reconfigurable time slot interchange (TSI) of individual bits at 40 Gb/s based on four-wave mixing (FWM) and a programmable planar lightwave circuit (PLC). The PLC is used to generate different control signals (masks) that determine which bits undergo TSI. By programming the PLC to generate two different masks, two different TSI patterns are obtained. TSI is achieved using FWM between the data signal and the desired mask with bidirectional propagation in a length of highly nonlinear fiber. Error-free operation is obtained for both of the TSI patterns, with a power penalty <; 5.2 dB, at a bit error rate of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-9</sup> .

Capability of single optical buffer loop implementing all-optical time slot interchange based on nonlinear polarization rotation in semiconductor optical amplifier

Based on nonlinear polarization rotation (NPR) in semiconductor optical amplifier (SOA), a single optical buffer loop theoretically and experimentally demonstrates its switch capability to realize all-optical time slot interchange (TSI) on multiple optical packets (MOPs). Firstly, a series of prerequisites is theoretically deduced with a single optical buffer loop performing all-optical TSI on MOPs. And the corresponding equations which experimental parameters should satisfy are derived from these prerequisites for different cases of all-optical TSI. Accounting to the theoretical results, a single optical buffer loop based on NPR in SOA experimentally realizes all-optical TSI on three packets and four packets at data rate of 10 Gb/s. Experimental results are in accordance with those expected theoretically. These results will be very helpful to make all-optical TSI system more compact and more highly efficient, and have less expensive elements such as SOA, and also significant for developing the all-optical TSI technology.

Experimental investigation of all-optical packet-level time slot assignment using two optical buffers cascaded

We proposed and experimentally demonstrated all-optical packet-level time slot assignment scheme with two optical buffers cascaded. The function of time-slot interchange (TSI) was successfully implemented on two and three optical packets at a data rate of 10 Gb/s. Therefore, the functions of TSI on N packets should be implemented easily by the use of N-1 stage optical buffer. On the basis of the above experiment, we carried out the TSI experiment on four packets with the same two-stage experimental setup. Furthermore, packets compression on three optical packets was also carried out with the same experimental setup. The shortest guard time of the packets compression can reach to 13 ns due to the limit of FPGA's control accuracy. Due to the use of the same optical buffer, the proposed scheme has the advantages of simple and scalable configuration, modularization, and easy integration.

A novel optical burst mesh network with optical time slot interchange at source nodes

In this paper, we propose an optical burst network architecture supporting the generic mesh topology. The intermediate node architecture of the mesh network can be the same with current wavelength switching Wavelength Division Multiplexing (WDM) networks, and thus can reuse existing deployed infrastructure. We employ a novel Optical Time Slot Interchange (OTSI) at the source nodes for the first time to mitigate the burst contention and to increase the bandwidth utilization. Time- and wavelength-domain reuse in the OTSI significantly saves optical components and reduces blocking probability.

All-Optical Time Slot Interchange Using a Cascaded Optical Buffer

A novel scheme of all-optical time slot interchanger employing two cascaded re-circulating optical buffers based on nonlinear polarization rotation in semiconductor optical amplifiers is proposed. The experimental system exhibits full interchangeable capability on three 512-bit packets at 10 Gbits/s. Theoretically, each packet length is up to 123ns with the maximum buffer depth 30%.

Field Experiments With a Grooming Switch for OTDM Meshed Networking

Field experiments of 42.7/128.1 Gb/s wavelength-division multiplexed, optical time-division multiplexed (WDM-OTDM) transmultiplexing and all-optical dual-wavelength regeneration at the OTDM rate are presented in this paper. By using the asynchronous retiming scheme, we achieve error-free bufferless data grooming with time-slot interchange capability for OTDM meshed networking. We demonstrate excellent performance from the system, discuss scalability, applicability, and the potential reach of the asynchronous retiming scheme for transparent OTDM-domain interconnection.

Dr. Hiroshi Inose's pioneering contributions to digital switching systems and his outstanding leadership in informatics

The idea of time slot interchange (TSI), the fundamental concept of implementing time switches in digital switching systems, was first conceived by Dr. Hiroshi Inose, then at the University of Tokyo, Japan, in 1957 while he was a visiting consultant at Bell Telephone Laboratories. The TSI collects each subscriber's pulse code modulation (PCM)-coded voice information to be stored into a small time interval (time slot), and then aligns multiple time slots on a common transmission bus to constitute a repetitive frame. The TSI enables any time slot to be interchanged with another time slot within a frame once the time slots in the frame are buffered in memories. Thus, TSI gives the time switch functionality equivalent to N-input by N-output space switch functionality. He built a prototype digital time-division multiplexing (TDM) electronic switching system called CAMPUS, which is based on the TSI principle, using a magnetostrictive delay line as a memory device. TSI received little attention until the end of the 1960s because memory devices were very costly. However, with the rapid advancement of semiconductor technologies in the 1970s, the TSI scheme became more widespread. TSI was first commercially deployed in 1976 as the time switch of AT&T's no. 4 ESS, the world's first stored-program control time-division switching system. Since then, TSI has been used in almost all digital central office switching systems and digital private branch exchanges (PBXs). Dr. Inose's contributions were not limited to research on such things as switching systems, PCM integrated communications, computer communications, and road traffic control systems; he was also actively involved in a number of Japanese governmental and international activities in the area of communications and information processing technologies. His final work was the establishment of the National Institute of Informatics (NII) in 2000, Japan's sole comprehensive academic institute in the field of informatics that seeks to advance integrated research and development activities in information-related fields.

Time-slot interchange of 40 Gbits/s variable length optical packets using conversion–dispersion-based tunable delays

We demonstrate tunable time-slot interchange of 40 Gbits/s optical data packets using a conversion-dispersion-based tunable optical delay element. Odd and even data packets are extracted from an input signal, delayed relative to one another in a highly dispersive medium, and then multiplexed back together. Tunability is demonstrated by operating with two different packet lengths, 182 and 288 bits/packet, and a bit error rate of <10(-9) is achieved.

On the space reuse efficiency of TSI-free OTDM rings

Design of future OTDM (optical time-division multiplexing) rings may require the network nodes to perform the time-slot interchange (TSI) function of moving data from an incoming time-slot to different outgoing time-slots. An efficient optical buffer technology for optical TSI is not currently available. Our previous work has shown that without TSIs, all slots in an OTDM rings will form equal-length cycles. In this letter, we derive a general formula that shows the relationship between the cycle length and the space reuse efficiency of a TSI-free OTDM bi-directional ring.

An Architecture for TSI-Free Nonblocking Optical TDM Switches

One of the key elements in building a time-division- multiplexed (TDM) switch is the time slot interchange (TSI). Given the current optical switching and buffer technologies, TSI-based TDM architectures have many implementation drawbacks, including severe signal attenuation. Some studies showed that some space-time equivalence diagrams can be converted into a delay-unit-based (TSI-free) TDM. This type of architecture is attractive for optical TDM switches, but the techniques discussed in those studies are for rearrangeable switches. Many applications require nonblocking switches where adding a new connection (or a flow) will not cause rearrangement of existing connections. In this paper, we present the design principle for building strictly nonblocking delay-unit-based (TSI-free) optical TDM switches.

Time-slot interchange using an optical buffer with a large variable delay range based on an active-vertical-coupler crosspoint switch

Time-slot interchange is investigated using an optical buffer with a large variable delay based on an active-vertical-coupler crosspoint switch. The delay could range from 1 to 999 time slots in our scheme, and the length of the time slot is correspondingly flexible. The experiment could be performed at a data rate of 10 Gbit/s. The results show the power penalty is about 1.5 and 5.6 dB, respectively, when the packets pass through two buffers and through one buffer nine times

Time-slot assignment using optical buffer with a large variable delay range based on AVC crosspoint switch

Time-slot assignment (TSA) functions including time-slot interchange and serial-to-parallel and parallel-to-serial conversions, and optical compressor are investigated using an optical buffer with a large variable delay range based on active vertical coupler crosspoint switch. The variable delay range could be achieved from 1 to 999 time slots in the proposed scheme, and correspondingly, the length of time slot is flexible. It is demonstrated that the experiments could be performed even at a data rate of 10 Gb/s with power penalties of about 1.5 and 5.6 dB compared with back-to-back when the packets pass through two buffers and one buffer nine times

Cell-sorting device for creating synchronous variable-length optical packet switches

We consider the design of a synchronous variable-length optical packet switch. Fixed-length packet switches may be used to switch variable-length packets if the packets are first divided into multiple fixed-length cells. However, for many fixed-length switch architectures, cells from multiple packets will become interspersed, and packet integrity will not be preserved. We describe the design of a fiber-delay-line-based cell sorter that when appended to the output of a fixed-length packet switch converts the switch into a variable-length packet switch by enabling variable-length packets to exit contiguously. We describe two implementations of the cell sorter. The first is simply a bank of delay lines. The second uses two stages of time-slot interchange and reduces the number of delay line elements to be a logarithmic function of the maximum packet length. We also estimate the packet-blocking probabilities of the resulting variable-length packet switch and verify our results via simulation.

Tunable all-optical time-slot-interchange and wavelength conversion using difference-frequency-generation and optical buffers

In this letter, we demonstrate a module that simultaneously performs optical time-slot interchange and wavelength conversion of the bits in a 2.5-Gb/s data stream to achieve a reconfigurable time/wavelength switch. Our switch uses difference-requency-generation (DFG) for wavelength conversion and fiber Bragg gratings as wavelength-dependent optical time buffers. This tunable technique employs high-extinction-ratio and low-additive-noise DFG.

Photonic time-slot and wavelength-grid interchange for 10-Gb/s packet switching

A time-space-wavelength-division photonic packet switch is proposed. The switch is based on ultrafast simultaneous time-slot and wavelength-grid interchange of optical packets using data-signal-induced supercontinuum (SC) light and arrayed waveguide gratings to slice the SC light spectrum. The switch was demonstrated at a data rate of 10 Gb/s.

Design of packet-switched network using optical signal processing techniques

In this paper, we design an optical packet-switched network with an optical ring resonator (ORR), a delay line decoder (DLD), and an optical address translator (OATR). The ORR can discriminate the header/payload directly in the optical domain. The DLD, together with the optical threshold device, can be used as an optical correlator for the routing control signal. The OATR uses time-slot-interchange (TSI) technology to translate the optical address for the next optical switching stages. These optical signal processing techniques can be applied to future high-speed all-optical switching networks. ©1999 John Wiley & Sons, Inc. Microwave Opt Technol Lett 23: 104–109, 1999.

Time-variant linear pulse processing

Previously suggested systems for linear processing of temporal pulses are limited to time-invariant (convolution-type) operations. Although these are the most general operations possible with passive components, we show that by using nonlinear optical interactions, arbitrary linear operations can be performed. Such operations may be useful for performing time-variant analog signal processing, temporal matrix-vector multiplication3 and time-slot interchange of pulses for digital communications systems.

A high performance switch for OC-12 SONET self-healing ring networks

The progress of ITU-T and ANSI standards on SDH/SONET is accelerating the evolution of transmission systems all over the world. The advanced operation administration and maintenance (OAM) functions it provides makes it possible to create a self healing ring network which protects against failure. This self-healing ring consists of add/drop multiplexers (ADM's). The switch in the ADM plays an important role in achieving self-healing operation. In this paper, self-healing ring architecture and operations are analyzed in order to determine the requirements for the ADM switch. On the basis of this result, new space division switching methods, which significantly reduce the amount of hardware needed, are proposed. A parallel processing architecture which makes it possible to develop a low-cost large-scale switch is also devised. Finally, a developed switch LSI chip is presented. Combining two identical chips with the proposed parallel processing architecture, a 32/spl times/32 STS-3 switch (5 Gb/s throughput) with an STS-1 time slot interchange (TSI) function is realized.