Many applications such as Industrial Internet of Things (IIoT), tactile Internet, and 5G/6G mobile require Ultra-Low Latency (ULL) in data transmission. The end-to-end latency is required to be on the order of sub-millisecond in these applications. The IEEE 802.1 Time Sensitive Networking (TSN) standards have been developed to provide ULL networking. The IEEE 802.1Qbv Time-Aware Shaper (TAS), which is a typical flow control mechanism of TSN, is a traffic shaper to provide deterministic end-to-end ULL transmission for express traffic. The Gate Control List (GCL) of all TAS enabled nodes must be configured in a coordinated manner to ensure ULL. However, existing configuration schemes cannot be employed in highly dynamic conditions where the distribution of time-sensitive streams frequently changes. It will be a significant problem to deal with such dynamic conditions in the future. Therefore, this paper proposes a real-time adaptive gate scheduling scheme for TAS. The scheduling problem is formulated as a boolean satisfiability problem (SAT), and the employment of an FPGA-based solver is proposed to achieve runtime fast computation. The proposed scheme enables real-time reconfiguration for high flexibility and high bandwidth utilization to deal with the dynamics of network conditions. The feasibility of the proposed scheme is confirmed with computer simulations.