Time-dependent Dielectric Breakdown Research Articles

Atomic diffusion and electrical reliability of NiAl/SiO2 interconnect: Breakdown voltage and TDDB characteristics

This study reports the effects of post-annealing on the electrical reliability of a NiAl/SiO2 interconnect structure for potential use as post-Cu interconnect. Our materials characterization using transmission electron microscopy and secondary ion mass spectrometry discloses that annealing at elevated temperatures induced the diffusion of Al into SiO2: Al, for a 400 °C-annealed sample, diffused only to a few nanometers from the interface, forming a thin aluminum-rich oxide layer, while samples annealed at higher temperatures show an extensive Al diffusion and interfacial reactions. In a voltage ramp dielectric breakdown test, the 400 °C annealed sample shows the lowest breakdown voltage, possibly, due to the aluminum-rich oxide layer serving as a self-forming barrier while the samples annealed at higher temperatures display a drastic reliability degradation with the annealing temperature increasing. In addition, analyzing data acquired from time-dependent dielectric breakdown tests using the E-model helps us predict the lifetime of the 400 °C sample to be longer than 105 h at 1 MV/cm.

An analog to digital converter in a SiC CMOS technology for high-temperature applications

Integrated circuits based on wide bandgap semiconductors are considered an attractive option for meeting the demand for high-temperature electronics. Here, we report an analog-to-digital converter fabricated in a silicon carbide complementary metal–oxide–semiconductor technology now available through Europractice. The MOSFET component in this technology was measured up to 500 °C, and the key parameters, such as threshold voltage, field-effect mobility, and channel-length modulation parameters, were extracted. A 4-bit flash data converter, consisting of 266 transistors, is implemented with this technology and demonstrates correct operation up to 400 °C. Finally, the gate oxide quality is investigated by time-dependent dielectric breakdown measurements at 500 °C. A field-acceleration factor of 4.4 dec/(MV/cm) is obtained by applying the E model.

Leakage and Thermal Reliability Optimization of Stacked Nanosheet Field-Effect Transistors with SiC Layers.

In this work, we propose a SiC-NSFET structure that uses a PTS scheme only under the gate, with SiC layers under the source and drain, to improve the leakage current and thermal reliability. Punch-through stopper (PTS) doping is widely used to suppress the leakage current, but aggressively high PTS doping will cause additional band-to-band (BTBT) current. Therefore, the bottom oxide isolation nanosheet field-effect transistor (BOX-NSFET) can further reduce the leakage current and become an alternative to conventional structures with PTS. However, thermal reliability issues, like bias temperature instability (BTI), hot carrier injection (HCI), and time-dependent dielectric breakdown (TDDB), induced by the self-heating effect (SHE) of BOX-NSFET, become more profound due to the lower thermal conductivity of SiO2 than silicon. Moreover, the bottom oxide will reduce the stress along the channel due to the challenges associated with growing high-quality SiGe material on SiO2. Therefore, this method faces difficulties in enhancing the mobility of p-type devices. The comprehensive TCAD simulation results show that SiC-NSFET significantly suppresses the substrate leakage current compared to the conventional structure with PTS. In addition, compared to the BOX-NSFET, the stress reduction caused by the bottom oxide is avoided, and the SHE is mitigated. This work provides significant design guidelines for leakage and thermal reliability optimization of next-generation advanced nodes.

Modeling of Charge-to-Breakdown with an Electron Trapping Model for Analysis of Thermal Gate Oxide Failure Mechanism in SiC Power MOSFETs.

The failure mechanism of thermal gate oxide in silicon carbide (SiC) power metal oxide semiconductor field effect transistors (MOSFETs), whether it is field-driven breakdown or charge-driven breakdown, has always been a controversial topic. Previous studies have demonstrated that the failure time of thermally grown silicon dioxide (SiO2) on SiC stressed with a constant voltage is indicated as charge driven rather than field driven through the observation of Weibull Slope β. Considering the importance of the accurate failure mechanism for the thermal gate oxide lifetime prediction model of time-dependent dielectric breakdown (TDDB), charge-driven breakdown needs to be further fundamentally justified. In this work, the charge-to-breakdown (QBD) of the thermal gate oxide in a type of commercial planar SiC power MOSFETs, under the constant current stress (CCS), constant voltage stress (CVS), and pulsed voltage stress (PVS) are extracted, respectively. A mathematical electron trapping model in thermal SiO2 grown on single crystal silicon (Si) under CCS, which was proposed by M. Liang et al., is proven to work equally well with thermal SiO2 grown on SiC and used to deduce the QBD model of the device under test (DUT). Compared with the QBD obtained under the three stress conditions, the charge-driven breakdown mechanism is validated in the thermal gate oxide of SiC power MOSFETs.

A newly developed Cu(Rh) alloy film and its characteristics and applications

A new type of copper (Cu)-rhodium (Rh)-alloy, Cu(Rh), films is developed by co-sputtering copper and rhodium onto silicon (Si) substrates under an argon (Ar) atmosphere. The new films are next annealed at 600 and 670 °C, or alternatively at 100 and 450 °C, for 1 h. Longer annealing to the films, for up to 8 days, is also conducted to explore resistivity variation. The resistivity of the new 300-nm-thick film is 2.19 μΩ cm after annealing at 670 °C for 1 h and drifts to 2.26 and 2.14 μΩ after annealing at 400 and 450 °C, respectively, for 200 h. A 2.7-μm-thick Sn layer is then thermally evaporated atop the new film for stable flip-chip solder joints; their metal and Cu-Sn intermetallic compound (IMC) growth processes vs. various annealing periods are tested. After annealing at 670 °C, the new 300-nm-thick film’s adhesive strength reaches 44.2 ± 0.01 MPa, which is 11 ~ 12-fold that of their pure Cu counterpart. Some key test results of the new film are disclosed herein, including its X-ray diffraction (XRD) patterns, transmission electron microscopy (TEM) images, secondary-ion mass spectrometry (SIMS), time-dependent dielectric-breakdown (TDDB) lifetime curves, and adhesive strength. The new film’s antibacterial efficacy arrives at an antibacterial ratio of approximately 100% against Staphylococcus aureus (S. aureus) BCRC 10451 for the 300-nm-thick film and approximately 99.82% for the 8 nm film, far superior to that of a pure Cu film, which is 0 with the same annealing temperature range. The new film, hence, seems to be a remarkable candidate material for various industrial applications, such as ultra-large-scale integrated circuits (ULSIC), micro-electronic circuits, printed circuits, flip-chip technology, medical care concerning antibacteria, and the like.Graphical A new type of copper (Cu)-rhodium (Rh)-alloy, Cu(Rh), films is developed by co-sputtering copper and rhodium onto silicon (Si) substrates under an argon (Ar) atmosphere and then annealing the new films at 600 and 670 °C, or alternatively at 100 and 450 °C, for 1 h. Longer annealing to the films, for up to 8 days, is also conducted to explore resistivity variation. The resistivity of the new 300-nm-thick film is 2.19 mW cm after annealing at 670°C for 1 h and drifts to 2.26 and 2.14 mW after annealing at 400 and 450 °C, respectively, for 200 h. A 2.7-μm-thick Sn layer is next thermally evaporated atop the new film for stable flip-chip solder joints; their metal and Cu-Sn intermetallic compound (IMC) growth processes vs. various annealing periods are tested. After annealing at 670°C, the new 300-nm-thick film’s adhesive strength reaches 44.2 ± 0.01 MPa, which is 11~12-fold that of their pure Cu counterpart. Some key test results of the new film are disclosed herein, including its X-ray diffraction (XRD) patterns, transmission electron microscopy (TEM) images, secondary-ion mass spectrometry (SIMS), time-dependent dielectric-breakdown (TDDB) lifetime curves, and adhesive strength. The new film’s antibacterial efficacy arrives at an antibacterial ratio of approximately 100% against Staphylococcus aureus (S. aureus) BCRC 10451 for the 300-nm-thick film and approximately 99.82% for the 8-nm film, far superior to that of a pure Cu film, which is 0 with the same annealing temperature range. The new film, hence, seems to be a remarkable candidate material for various industrial applications, such as ultra-large-scale integrated circuits (ULSIC), micro-electronic circuits, printed circuits, flip-chip technology, medical care concerning antibacteria, and the like.

Breakdown voltage and TDDB performance improvement by optimizing the PECVD dielectric film characteristics in MIM capacitors

The dielectric breakdown voltage (BV) and time dependent dielectric breakdown (TDDB) are the most important concerns for device reliability. In this study, the silicon nitride (SiNx) used as metal-insulator-metal (MIM) capacitor dielectric was successfully prepared by a dual-frequency plasma enhanced chemical vapor deposition (PECVD) method. Fourier transform infrared (FTIR) absorption spectra and electrical characterization results suggest that the SiNx film possesses higher dielectric breakdown voltage performance by decreasing SiH4/NH3 gas flow ratio or optimizing the interface layer among multiple layers. Similarly, the TDDB reliability test based on Weibull distribution indicates an increase in failure lifetime of the MIM capacitors by adjusting RF power and NH3 gas flow.

Improved Vth Stability and Gate Reliability of GaN-Based MIS-HEMTs by Employing Alternating O2 Plasma Treatment.

The Vth stability and gate reliability of AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) with alternating O2 plasma treatment were systematically investigated in this article. It was found that the conduction band offset at the Al2O3/AlGaN interface was elevated to 2.4 eV, which contributed to the suppressed gate leakage current. The time-dependent dielectric breakdown (TDDB) test results showed that the ALD-Al2O3 with the alternating O2 plasma treatment had better quality and reliability. The AlGaN/GaN MIS-HEMT with the alternating O2 plasma treatment demonstrated remarkable advantages in higher Vth stability under high-temperature and long-term gate bias stress.

SPICE simulation of the time-dependent clustering model for dielectric breakdown

In this letter, a method for dealing with the time-dependent dielectric breakdown (TDDB) of oxide layers in MOS and MIM structures in the framework of SPICE simulations is reported. In particular, we focus the attention on the clustering model (Burr’s XII distribution) for dielectric breakdown which can be considered an extension of the well known Weibull model. The oxide time-to-breakdown for both models is calculated using the inversion method for the cumulative distribution function. For the sake of completeness, the proposed approach includes uncorrelated variability both in the initial and final resistance states. For illustrative purposes, it is also shown how voltage acceleration, progressive breakdown or any other correlation factor can be introduced in the simulation parameters. As an application example, the proposed method is used to simulate the simplest case of a gate-to-drain dielectric breakdown of a NMOS-based inverter circuit.

Dielectric breakdown behavior of ferroelectric HfO2 capacitors by constant voltage stress studied by in situ laser-based photoemission electron microscopy

In situ laser-based photoemission electron microscopy observations with time-dependent dielectric breakdown measurements of TiN/Hf0.5Zr0.5O2(HZO)/TiN ferroelectric capacitors were performed to reveal the dielectric breakdown (DB) mechanism. We succeeded in visualizing the hard DB spots through the top electrode. We found that capacitors with short- and long-lifetime distributions were broken down near and far from the edge of the capacitors, respectively. This indicates that the DB is either topography-dependent or film-quality-dependent. This work demonstrates an effective method of detecting DB in a non-destructive manner to provide an insight for achieving higher endurance HfO2-based ferroelectric capacitors.

Graphene-All-Around Cobalt Interconnect with a Back-End-of-Line Compatible Process.

The graphene-all-around (GAA) structure has been verified to grow directly at 380 °C using hot-wire chemical vapor deposition, within the thermal budget of the back end of the line (BEOL). The cobalt (Co) interconnects with the GAA structure have demonstrated a 10.8% increase in current density, a 27% reduction in resistance, and a 36 times longer electromigration lifetime. X-ray photoelectron spectroscopy and density functional theory calculations have revealed the presence of bonding between carbon and Co, which makes the Co atom more stable to resist external forces. The ability of graphene to act as a diffusion barrier in the GAA structure was confirmed through time-dependent dielectric breakdown measurement. The Co interconnect within the GAA structure exhibits enhanced electrical properties and reliability, which indicates compatibility applications as next-generation interconnect materials in CMOS BEOL.

Time-dependent dielectric breakdown of SiC-CMOS technology for harsh environments

To estimate the failure time of silicon carbide (SiC) integrated circuits in harsh environments, the activation energy (Ea) and field acceleration factor of SiC n-channel MOS (nMOS) and p-channel MOS (pMOS) were measured using time-dependent dielectric breakdown testing at constant voltage stress in the range of 25–350 °C. Ea around 300 °C was 0.7 eV for nMOS and 0.66 eV for pMOS, which was about twice as high as that below 150 °C and did not differ greatly depending on the conductivity type. The gate dielectric breakdown mechanism shifted from the 1/E model to the E model as the temperature rose, and this is thought to have caused the Ea to change. The field acceleration factor in the E model at 300 °C was 2.7 and 2.3 cm/MV for nMOS and pMOS, respectively. The maximum operating electric fields of nMOS and pMOS for a 100-year lifetime are 6.8 and −7.2 MV/cm, which are over 25% lower than the fields at room temperature, mainly due to a shift in the dominant breakdown model. A more conservative failure time design will be required for SiC-ICs exposed to high temperatures.

The Understanding and Compact Modeling of Reliability in Modern Metal-Oxide-Semiconductor Field-Effect Transistors: From Single-Mode to Mixed-Mode Mechanisms.

With the technological scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs) and the scarcity of circuit design margins, the characteristics of device reliability have garnered widespread attention. Traditional single-mode reliability mechanisms and modeling are less sufficient to meet the demands of resilient circuit designs. Mixed-mode reliability mechanisms and modeling have become a focal point of future designs for reliability. This paper reviews the mechanisms and compact aging models of mixed-mode reliability. The mechanism and modeling method of mixed-mode reliability are discussed, including hot carrier degradation (HCD) with self-heating effect, mixed-mode aging of HCD and Bias Temperature Instability (BTI), off-state degradation (OSD), on-state time-dependent dielectric breakdown (TDDB), and metal electromigration (EM). The impact of alternating HCD-BTI stress conditions is also discussed. The results indicate that single-mode reliability analysis is insufficient for predicting the lifetime of advanced technology and circuits and provides guidance for future mixed-mode reliability analysis and modeling.

(Invited) On the Advantage of Deploying ALD-Deposited Gate Oxides for 4H-Silicon Carbide MOS Applications

The wide bandgap semiconductor material 4H-silicon carbide (SiC) has revolutionized the power electronics device market since the commercialization of the first SiC metal-oxide-semiconductor field-effect transistor (MOSFET) in 2012. In the blocking voltage range between 650V-1,700 V, SiC MOSFETs offer a higher maximum switching frequency, lower total space consumption as well as a higher temperature operation range than their silicon (Si) counterparts, e.g., the Si insulated-gate bipolar transistors (IGBT). This has led to the rapid uptake in deployment of SiC MOSFETs in main drivetrain inverter topologies in battery electric vehicles (BEVs).Given the importance the availability of oxides play in the role of any MOS-structure, the successful implementation of SiC MOSFETs into power electronics conversion stages has in no small part been due to its native oxide, silicon dioxide (SiO2). This can easily be thermally grown at temperatures between 1,100°C-1,400°C. This advantage as well as the relatively large conduction band offset of approx. 2.7 eV between SiC and SiO2 make SiO2 the ubiquitous gate oxide in any SiC device.However, interface defect densities are still much more prevalent in SiC/SiO2 systems than in their Si/SiO2 MOS counterparts, and most of these defects originate from the thermal oxidation process, which ends up forming carbon-rich interfaces containing carbon clusters, hydrogen (H) and oxygen (O) vacancies. These defects enhance scattering, increase leakage currents and hence reduce channel mobilities in MOSFETs. This is a major technological issue, leading to specific on-resistances (RON,SP) that are much higher than the theoretical unipolar limit of SiC would allow, hampering the further uptake of SiC MOS technology.In this investigation, we explore the three most used deposition/growth mechanisms that will form an SiO2 layer on SiC and the impact this mechanism will have on the interface quality and high-temperature reliability of MOS-based SiC devices.Lateral MOSFETs (LMOSFETs), metal-oxide-semiconductor capacitors (MOSCAPs) and all other mentioned device structures were fabricated on 10 μm thick, nitrogen-doped (4 x 1015 cm-3) epitaxial layers that were grown on highly nitrogen-doped SiC substrates. LMOSFET devices underwent a conventional implantation schedule for the p-base and n+-source and drain implant, both carried out at 500°C, with the post-implantation anneal carried out at 1,750°C for 45 minutes in Ar (5 slm).Once samples had undergone an initial solvent clean/RCA 1/HF (10%)/ RCA 2/HF (10%) clean procedure, a 1 μm thick field oxide was deposited on the samples through low-pressure chemical vapour deposition (LPCVD). A gate oxide window was opened by means of photolithography, after which the oxide was thinned down to a thickness of approximately 30 nm by means of reactive ion etching (RIE). The final oxide was removed using a wet etch in diluted 10% buffered oxide etch to prevent surface exposure to heavily accelerated and charged particles. The gate oxides were then put down using one of the following oxidation routines: ALD deposition of SiO2 using bis(diethylamino)silane (BDEAS) and an oxygen plasma at 200°C (750 cycles) orALD deposition of SiO2 using bis(diethylamino)silane (BDEAS) and an oxygen plasma at 200°C (750 cycles) plus a PDA in FG ambient (5 slm, 5 % H2) at 1,100°C for 1 h.LPCVD using tetraethyl orthosilicate (TEOS) as a precursor.Direct thermal growth at 1300°C for 5 hrs in diluted N2O (4 slm Ar: 1 slm N2O) ambient. Since samples that had undergone routines 1 and 3 usually show a poor as-deposited oxide quality, a post-deposition anneal was performed on these samples in an oxidation furnace in N2O ambient at 1,300°C for 2 hrs. All N2O treated samples (1,3 and 4) showed an oxide thickness of approximately 60 nm, with the FG-treated sample showing a lower thickness of approx. 35 nm. Conventional metal contact formation was then carried out to finalise the devices.In this investigation, we investigate the current-voltage (I-V), capacitance-voltage (C-V) and constant-voltage time dependent dielectric breakdown (TDDB) performance. We will present evidence that high-quality, highly reliable SiO2 layers, formed by ALD and PDA, can be created. Flatband voltage and hysteresis values will be reduced, compared to thermally grown oxides, and frequency dispersion in accumulation is negligible. The ALD oxide with forming gas PDA has the best performance across the entire dataset at all measured voltages (9.6 MV/cm, 9.3 MV/cm, 9 MV/cm, 8.5 MV/cm, 8 MV/cm). This is due to a different interface chemistry, shown by XPS, HRTEM and SIMS, where Si complexes, such as Si dimers or SixOy groups are broken down into simple Si dangling bonds, which can be readily passivated with a FG anneal. This will be discussed in detail in this talk. Figure 1

Investigation of time-dependent gate dielectric breakdown in recessed E-mode GaN MIS-HEMTs using ferroelectric charge trap gate stack (FEG-HEMT)

The aim of achieving E-mode operations has led to the proposal of novel hybrid ferroelectric charge trap gate stack schemes. These schemes involve utilizing a combination of the charge trapping layer (CTL) and the ferroelectric laminated layer to positively shift the threshold voltage to a normally-off margin after initializing the gate pulse, thus achieving the Enhancement-mode (E-mode) characteristic. This study focuses on the forward gate bias time-dependent dielectric breakdown (TDDB) gate reliability in the E-Mode GaN MIS-HEMTs using ferroelectric charge trap gate stack (FEG-HEMT) with and without recess and investigates the impact of temperature on TDDB. The gate voltages required for operation with a 1 % failure rate over a 10-year period are 12.95 V and 10.22 V at 25 °C and 150 °C for both samples, respectively. Also, the examination of the stability of the recessed process by calculating the activation energies (0.7 eV) of both samples are demonstrated. The article also investigates the relationship between long-term reliability and short-term initialization by examining the transition point of the time-dependent failure curve.

Reliability of the hybrid bonding level using submicrometric bonding pads

Hybrid bonding is a major enabler for devices requiring 3D stacking with high interconnection density. An in-depth reliability study is performed for the specific Cu/SiO2 integration to identify the potential failure mechanisms. A high robustness is evidenced down to bonding pitch 0.81 μm for the standard reliability tests such as Thermal Cycling (TC) tests, High Temperature Storage (HTS) test, Stress induced Voiding (SiV), Time Dependent Dielectric Breakdown (TDDB) or electromigration. The hybrid bonding interface is stable under thermal stress with no atomic or ionic Cu diffusion observed through the hybrid bonding interface. The role of the thin self-formed cuprous oxide at the Cu/SiO2 interface in the case of misaligned bonding pads is believed to play a major role in the high robustness to reliability tests.

Investigation of the time dependent gate dielectric stability in SiC MOSFETs with planar and trench gate structures

In this work, the time-dependent dielectric breakdown (TDDB) analysis is performed to understand the gate oxide reliability in SiC MOSFETs with two different structures, i.e., planar and trench gate structures. We have discovered different gate leakage current behaviors between the SiC MOSFETs with planar gate (Sample A) and trench gate (Sample B) during the forward gate bias stress. Notably, the slight increase of the gate current during the stress and the negative activation energy (Ea = −0.07 eV) observed in Sample A suggest that the hole generation caused by the impact ionization can be occurred during the forward gate TDDB tests. Furthermore, the SiC MOSFETs with trench gate structure (Sample B) exhibit the operation voltage of 55.7 V (exponential law) and 57.3 V (power law) for the 0.001 % failure of 30 years under 175 °C, indicating that SiC trench gate MOSFETs with enough thick gate dielectric (87.1 nm (bottom) and 77.9 nm (sidewall)) can have the promising forward gate TDDB stability.

Automated reliability calculation of failure rate, lifetime extrapolation and prediction for embedded Metal-Insulator-Metal capacitors using an optimized Time-Dependent-Dielectric-Breakdown model

This study presents an algorithm for automated reliability analysis of embedded Metal-Insulator-Metal (MIM) capacitors with high-k dielectrics. With the proposed algorithm, Time-Dependent-Dielectric-Breakdown (TDDB) data of embedded capacitors of different physical dimensions measured at various stress conditions (temperature and electric field) can be analyzed in a uniform way based on a supervised learning approach. Instead of analyzing each influence parameter separately, the data is combined using automated linear regression, based on decision tree learning and thus defining a multi-dimensional plane. With this approach a simultaneous consideration of all affecting parameters and their interaction on the dataset can be achieved, while removing statistical outliers and extrapolating the reliability behavior of any failure percentage. To support the most common conduction mechanism related to the embedded ΜΙΜ capacitors, Poole-Frenkel emission, a new TDDB model with changed coordinate system is proposed.

MoS2 as an Effective Cu Diffusion Barrier with a Back-End Compatible Process.

This study demonstrates molybdenum disulfide (MoS2) as a superior candidate as a diffusion barrier and liner. This research explores a newly developed process to show how effectively MoS2 can be applied. First, a new approach is developed to prepare molybdenum disulfide (MoS2) by microwave plasma-enhanced sulfurization (MW-PES). MW-PES can rapidly and directly grow on the target substrate at low temperatures, which is compatible with the back-end-of-line (BEOL) technology. Second, the performance of MW-PES MoS2 as a diffusion barrier and liner is reported in the subsequent section. Through time-dependent dielectric breakdown (TDDB) measurements, MoS2 is shown to have a barrier property better than that of the current material, Ta, with the same thickness. According to the model fitting, the lifetime of the device is about 45.2 times the lifetime under normal operating conditions. Furthermore, MoS2 shows its superior thermal stability in maintaining the barrier properties. MoS2 is proven to be an excellent interface as a liner as it can provide sufficient adhesion and wettability to further effectively reduce the surface scattering of copper (Cu) and significantly lower the circuit resistance.

Proton Irradiation-Induced Reliability Degradation of SiC Power MOSFET

The effect of 53 MeV proton irradiation on the reliability of silicon carbide power MOSFETs was investigated. Post-irradiation gate voltage stress was applied and early failures in time-dependent dielectric breakdown (TDDB) test were observed for irradiated devices. The applied drain voltage during irradiation affects the degradation probability observed by TDDB tests. Proton-induced single event burnouts (SEB) were observed for devices which were biased close to their maximum rated voltage. The secondary particle production as a result of primary proton interaction with the device material was simulated with the Geant4-based toolkit.

The Gate Oxide Breakdown Failures of 4H-SiC MOS Devices

A study of Weibull distribution of 4H-SiC MOS capacitors has shown the effect of temperature as well as electric-field stress on the analysis of time-dependent breakdown. Time-Dependent Dielectric Breakdown (TDDB) is strongly electric-field dependent and temperature-dependent. In the paper, the test was at the stress level of 9.5, 10, and 10.5 MV/cm under 373K, through the TDDB model, the lifetime of the SiO2 can reach more than 30 years when the field pressure is not more than 6.6 MV /cm. The acceleration factor for TDDB (using E-Model) under different temperature stress, it expected that the capacitors would last for 2.28×107 years under 3MV/cm or 54 years under 6MV/cm at 373K.