Time-dependent Dielectric Breakdown Tests Research Articles

Atomic diffusion and electrical reliability of NiAl/SiO2 interconnect: Breakdown voltage and TDDB characteristics

This study reports the effects of post-annealing on the electrical reliability of a NiAl/SiO2 interconnect structure for potential use as post-Cu interconnect. Our materials characterization using transmission electron microscopy and secondary ion mass spectrometry discloses that annealing at elevated temperatures induced the diffusion of Al into SiO2: Al, for a 400 °C-annealed sample, diffused only to a few nanometers from the interface, forming a thin aluminum-rich oxide layer, while samples annealed at higher temperatures show an extensive Al diffusion and interfacial reactions. In a voltage ramp dielectric breakdown test, the 400 °C annealed sample shows the lowest breakdown voltage, possibly, due to the aluminum-rich oxide layer serving as a self-forming barrier while the samples annealed at higher temperatures display a drastic reliability degradation with the annealing temperature increasing. In addition, analyzing data acquired from time-dependent dielectric breakdown tests using the E-model helps us predict the lifetime of the 400 °C sample to be longer than 105 h at 1 MV/cm.

Improved Vth Stability and Gate Reliability of GaN-Based MIS-HEMTs by Employing Alternating O2 Plasma Treatment.

The Vth stability and gate reliability of AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) with alternating O2 plasma treatment were systematically investigated in this article. It was found that the conduction band offset at the Al2O3/AlGaN interface was elevated to 2.4 eV, which contributed to the suppressed gate leakage current. The time-dependent dielectric breakdown (TDDB) test results showed that the ALD-Al2O3 with the alternating O2 plasma treatment had better quality and reliability. The AlGaN/GaN MIS-HEMT with the alternating O2 plasma treatment demonstrated remarkable advantages in higher Vth stability under high-temperature and long-term gate bias stress.

Time-dependent dielectric breakdown of SiC-CMOS technology for harsh environments

To estimate the failure time of silicon carbide (SiC) integrated circuits in harsh environments, the activation energy (Ea) and field acceleration factor of SiC n-channel MOS (nMOS) and p-channel MOS (pMOS) were measured using time-dependent dielectric breakdown testing at constant voltage stress in the range of 25–350 °C. Ea around 300 °C was 0.7 eV for nMOS and 0.66 eV for pMOS, which was about twice as high as that below 150 °C and did not differ greatly depending on the conductivity type. The gate dielectric breakdown mechanism shifted from the 1/E model to the E model as the temperature rose, and this is thought to have caused the Ea to change. The field acceleration factor in the E model at 300 °C was 2.7 and 2.3 cm/MV for nMOS and pMOS, respectively. The maximum operating electric fields of nMOS and pMOS for a 100-year lifetime are 6.8 and −7.2 MV/cm, which are over 25% lower than the fields at room temperature, mainly due to a shift in the dominant breakdown model. A more conservative failure time design will be required for SiC-ICs exposed to high temperatures.

Investigation of the time dependent gate dielectric stability in SiC MOSFETs with planar and trench gate structures

In this work, the time-dependent dielectric breakdown (TDDB) analysis is performed to understand the gate oxide reliability in SiC MOSFETs with two different structures, i.e., planar and trench gate structures. We have discovered different gate leakage current behaviors between the SiC MOSFETs with planar gate (Sample A) and trench gate (Sample B) during the forward gate bias stress. Notably, the slight increase of the gate current during the stress and the negative activation energy (Ea = −0.07 eV) observed in Sample A suggest that the hole generation caused by the impact ionization can be occurred during the forward gate TDDB tests. Furthermore, the SiC MOSFETs with trench gate structure (Sample B) exhibit the operation voltage of 55.7 V (exponential law) and 57.3 V (power law) for the 0.001 % failure of 30 years under 175 °C, indicating that SiC trench gate MOSFETs with enough thick gate dielectric (87.1 nm (bottom) and 77.9 nm (sidewall)) can have the promising forward gate TDDB stability.

Proton Irradiation-Induced Reliability Degradation of SiC Power MOSFET

The effect of 53 MeV proton irradiation on the reliability of silicon carbide power MOSFETs was investigated. Post-irradiation gate voltage stress was applied and early failures in time-dependent dielectric breakdown (TDDB) test were observed for irradiated devices. The applied drain voltage during irradiation affects the degradation probability observed by TDDB tests. Proton-induced single event burnouts (SEB) were observed for devices which were biased close to their maximum rated voltage. The secondary particle production as a result of primary proton interaction with the device material was simulated with the Geant4-based toolkit.

Improved Endurance of Ferroelectric Hf0.5Zr0.5O2 Using Laminated-Structure Interlayer.

In this article, the endurance characteristic of the TiN/HZO/TiN capacitor was improved by the laminated structure of a ferroelectric Hf0.5Zr0.5O2 thin film. Altering the HZO deposition ratio, the laminated-structure interlayer was formed in the middle of the HZO film. Although small remanent polarization reduction was observed in the capacitor with a laminated structure, the endurance characteristic was improved by two orders of magnitude (from 106 to 108 cycles). Moreover, the leakage current of the TiN/HZO/TiN capacitor with the laminated-structure interlayer was reduced by one order of magnitude. The reliability enhancement was proved by the Time-Dependent Dielectric Breakdown (TDDB) test, and the optimization results were attributed to the migration inhibition and nonuniform distribution of oxygen vacancies. Without additional materials and a complicated process, the laminated-structure method provides a feasible strategy for improving HZO device reliability.

Breakdown-limited endurance in HZO FeFETs: Mechanism and improvement under bipolar stress

Breakdown is one of main failure mechanisms that limit write endurance of ferroelectric devices using hafnium oxide-based ferroelectric materials. In this study, we investigate the gate current and breakdown characteristics of Hf0.5Zr0.5O2/Si ferroelectric field-effect transistors (FeFETs) by using carrier separation measurements to analyze electron and hole leakage currents during time-dependent dielectric breakdown (TDDB) tests. Rapidly increasing substrate hole currents and stress-induced leakage current (SILC)-like electron currents can be observed before the breakdown of the ferroelectric gate insulator of FeFETs. This apparent degradation under voltage stress is recovered and the time-to-breakdown is significantly improved by interrupting the TDDB test with gate voltage pulses with the opposite polarity, suggesting that defect redistribution, rather than defect generation, is responsible for the trigger of hard breakdown.

(Invited, Digital Presentation) Improved Reliability of 4H-SiC Metal-Oxide-Semiconductor Devices Utilising Atomic Layer Deposited Layers with Enhanced Interface Quality

A major component of reliability of Silicon Carbide (4H-SiC) power electronics are due to the gate dielectric. Specific aspects such as hysteresis, insulator lifetime, threshold voltage (VTH) instability and high leakage currents, remain an issue of paramount importance which hamper the uptake of 4H-SiC power MOSFETs.1 The oxide understood to have the most importance is coincidently the native oxide, SiO2, due to the suitable band offset to 4H-SiC. However, most of the SiO2/SiC interface problems, such as carbon clusters, H content and O vacancies, are directly related to the thermal oxidation process.2 Here, we show these issues can partially be avoided by using dielectric deposition instead.Atomic layer deposition (ALD) offers specific advantages such as very low deposition temperature, excellent process control and suitability for conformal deposition of gate oxides in trench structures.3 Deposited oxides still require a post-deposition anneal (PDA) in a nitrogen-containing ambient4 such as nitrous oxide (N2O) or nitric oxide (NO) [2] to passivate the defects within the stack and improve the as-deposited layer’s poor electrical quality. We present the excellent reliability performance of ALD-deposited SiO2 layers on SiC through fabrication of metal-oxide-semiconductor capacitors (MOSCAPs) and then using time-dependent dielectric breakdown (TDDB) characterisation. The distribution of interface parameters, as well as the results from TDDB, have been investigated as metrics of improvement following the N2O PDA process. For benchmarking, processes will be compared to thermally grown oxides4 and LPCVD-deposited dielectric layers to demonstrate the superior process quality.An active 10 µm thick epitaxial layer of 4 × 1015 cm-3 n-type doping is used in this study and grown on 100 mm diameter, 4° off-axis (0001) 4H-SiC wafers. Growth was performed using a 30 μm/hr growth and N2 as a dopant in an LPE ACiS M8 chemical vapour deposition (CVD) reactor. After an initial clean, a 1 µm thick field oxide was deposited and a window was opened via photolithography and reactive ion etching (RIE). Then, quarter wafers underwent one of the three oxidation routines: 1. SiO2 plasma deposition at 200 °C using bis(diethylamino)silane (BDEAS) and O2 plasma precursors in an Ultratech Fiji G2 Plasma-Enhanced ALD System. 2. SiO2 deposition at 750 °C using tetraethyl orthosilicate (TEOS) as a precursor in a Thermco LPCVD system. 3. direct thermal growth of SiO2 in a HiTech furnace at 1300 °C for 5 hrs in N2O ambient. Samples that had undergone one of the first two routines then underwent a PDA in N2O, in the HiTech furnace at 1300°C for 2 hrs. All oxidation measurements resulted in oxide thicknesses between 50 and 60 nm, which were verified using step-height AFM measurements and optical interferometry. To create the vertical MOSCAP structure samples had a 500 nm aluminium (Al) backside contact deposited, before a 1 μm Al layer was deposited on the topside of the samples by means of a liftoff process. A cross-sectional diagram of the fabricated final device structure is shown in Fig. 1 (a). Table I shows the key electrical parameters which were extracted using room temperature C-V measurements, combined with I-V and constant field TDDB measurements at 175 °C. Fig. 1 (b) shows the improvement brought about by the N2O anneal, which also results in the average flatband voltage being reduced by more than 10 V to the lowest value of the dataset (1.44 V) and frequency dispersion mostly removed, with all but the ALD as-deposited samples reaching average breakdown oxide fields of about 10 MV/cm. The most promising improvement of the ALD-deposited SiO2 can be seen observing the breakdown distribution of MOSCAPs when stressed at constant high electric field (9 MV/cm), which can be seen in Fig. 2 (a) and (b). Here, these samples reach a TDDB, 63% value of 4786 s, which represents an average increase of 28% when compared to LPCVD samples and 58% when comparing this to a purely thermal process.Further evidence will be presented that high-quality, high-reliability SiO2 layers, formed by ALD and PDA have been formed. Flatband voltage and hysteresis are reduced, compared to thermally grown oxide, and frequency dispersion in accumulation is negligible. The ALD oxide with PDA has higher reliability than LPCVD and thermal oxides in TDDB tests, offering 29% to 345% improvement. The degradation mechanisms of the ALD oxide are different to that the LPCVD and thermal oxides and will be discussed in this talk.[1] P. Moens et al, ISPSD 32, 78-71 (2020).[2] P. Fiorenza et al, Appl. Surf. Sci., 149752 (2021).[3] A. Renz et al, MSSP 122, 105527 (2021).[4] K. Tachiki et al, Appl. Phy. Expr. 13.12, 121002(2020). Figure 1

Effect of N2-Anneal Temperature on Silicon Nitride Film: (I) Time-Dependent Dielectric Breakdown and ESR Evaluations

Silicon Nitride (SiN) film has been used as insulating material in many electronic devices such as capacitors and memories . In this report, the effect of N2 anneal temperature on charge break down (Qbd) of LP-CVD SiN film was electrically evaluated using the time-dependent dielectric breakdown (TDDB) test method, and the variation and the density of defects which exist in SiN film, in the oxide layer between SiN and Si substrate, and at the surface of Si substrate, were investigated using an Electron Spin Resonance (ESR) to reveal the defect behavior related to the trigger of Qbd.SiN metal-insulator-metal (MIM) capacitors were fabricated to evaluate TDDB. A 54 nm dielectric layer of SiN film was deposited at 700 degree-C, using a mixture of dichlorosilane（SiH2Cl2）and ammonia (NH3) gasses, by a LP-CVD vertical furnace. For the lower and upper electrode, a 400 nm polycrystalline silicon films were deposited using a LP-CVD. In order to evaluate the effect of anneal temperature on SiN film breakdown frequency, these samples were annealed in nitrogen atmosphere at temperatures between 700 and 1150 degree-C for 1 hour, using a vertical furnace.Breakdown voltage was measured with a current-voltage tester (HP4071A, Hewlett Packard) for each SiN MIM capacitor. The breakdown frequency was defined as the ratio of failed capacitors to tested capacitors. For the TDDB measurements, a constant current stress of 1.33 A/cm2 was applied to the MIM capacitors with the area of 0.00375cm2, 0.0075cm2, 0.015cm2 and 0.03cm2. For each area, 100 chips were made from one wafer and measured.In Fig.1, SiN film breakdown frequency increases toward a peak at around the N2 anneal temperature of 900 degree-C, then decreases at 1000 degree-C, and at more than 1100 degree-C, the frequency increases again drastically at 1150 degree-C.SiN films for ESR study were fabricated on Si wafer in the same LP-CVD process, and annealed in nitrogen atmosphere at temperatures between 700 and 1150 degree-C for 1 hour, using a vertical furnace.The ESR measurements were performed at room temperature using an X-band spectrometer (JES-RE1X). To improve the signal-to-noise ratio of an ESR signal waveform, we set the accumulation number of magnetic-field (H) sweep about 300 times. Mn2+/ MgO hyperfine lines were used for the g marker, and spin densities were determined by using the standard of known spin content.In Fig.2, Dangling bond density at silicon interface (Pb center) has a peak at 900 degree-C, and those in SiO2 (E’ center) and SiN film (K center) increase with increasing temperature from 1000 to 1150 degree-C. The former phenomena of Pb center coincides with the peak of SiN film breakdown frequency at 900 degree-C, and the latter one of E’ center and K center coincides with the tendency of increasing Qbd frequency at more than 1000 degree-C. Figure 1

Effect of N2-Anneal Temperature on Silicon Nitride Film: (I) Time-Dependent Dielectric Breakdown and ESR Evaluations

Silicon Nitride (SiN) film has been used as insulating material in many electronic devices such as capacitors and memories. This report electrically evaluated the effect of N2 annealing temperature on accidental charge breakdown (Qbd) of LP-CVD SiN film using the time-dependent dielectric breakdown (TDDB) test method. The variation and number of the defects, existing in the SiN film, in the oxide layer between SiN film and Si substrate, and at the SiN film/Si interface, were investigated using an electron spin resonance (ESR) to reveal the defect behavior related to triggering Qbd. At Si surface (Pb center), dangling bond density reached a maximal peak at an annealing temperature of 900°C, and those in SiO2 film (E′ center) and SiN film (K center) were increased with increasing temperature above 1000°C. These two types of phenomena showed good agreement with the Qbd occurrence dependency on the annealing temperature, as the detected by TDDB.

Electrical overstress effect characterization on Power MOS Trenchfet and correlation with time dependent dielectric breakdown

In recent years, power electronics has played a fundamental role in the development of increasingly efficient circuits for energy conversion. The characterization of a Power MOSFET under a gate overstress and the correlation with the reliability performances represent a crucial point in the optimization of the trench technology where the oxidation processes of the gate oxide are critical in terms of uniformity and reproducibility of the thickness. This article explores these aspects with particular attention to the analysis of the electrical overstress effect on aging transistors parameters and the classical TDDB (time dependent dielectric breakdown) test for gate oxide integrity characterization and lifetime extrapolation.The latter actually trigger oxide breakdown which is not as relevant at operating conditions as parametric degradation which usually occurs much earlier.Moreover, a possible physical explanation to the adherence of both failure modes (breakdown and transistor aging) to the two typical failure model such as thermochemical model and anode hole injection has been subjected to analysis following fitting methods as did in the past including their reciprocal correlation.

Impact of STI indium implantation on reliability of gate oxide

The impacts of shallow trench isolation (STI) indium implantation on gate oxide and device characteristics are studied in this work. The stress modulation effect is confirmed in this research work. An enhanced gate oxide oxidation rate is observed due to the enhanced tensile stress, and the thickness gap is around 5%. Wafers with and without STI indium implantation are manufactured using the 150-nm silicon on insulator (SOI) process. The ramped voltage stress and time to breakdown capability of the gate oxide are researched. No early failure is observed for both wafers the first time the voltage is ramped up. However, a time dependent dielectric breakdown (TDDB) test shows more obvious evidence that the gate oxide quality is weakened by the STI indium implantation. Meanwhile, the device characteristics are compared, and the difference between two devices is consistent with the equivalent oxide thickness (EOT) gap.

Effect of Phosphorus Doped Poly Annealing on Threshold Voltage Stability and Thermal Oxide Reliability in 4H-SiC MOSFET

We have investigated the effect of high temperature annealing of phosphorus doped poly on gate oxide integrity and device reliability. In NMOS capacitance analysis, unstable flat band voltage characteristics and lower oxide breakdown electric field were observed in wafers which received high temperature poly annealing at 1100 °C. Gate oxide integrity (GOI/Vramp) tests and time dependent dielectric breakdown (TDDB) tests were performed to evaluate wafer level reliability. Degraded GOI characteristics and poor gate oxide lifetime were obtained for the high temperature poly annealed condition. To evaluate package level reliability, high temperature gate bias (HTGB) stress tests were conducted. Some samples failed in positive gate bias stress and more severe negative threshold voltage shift was observed in negative gate bias stress for the high temperature poly annealed condition.

Gate Oxide Reliability of SiC MOSFETs and Capacitors Fabricated on 150mm Wafers

Gate oxide reliability on silicon carbide MOSFETs and large-area SiC N-type capacitors was studied for devices fabricated on 150mm SiC substrates. Oxide lifetime was measured under accelerated stress conditions using constant-voltage time-dependent dielectric breakdown (TDDB) testing, or ramped-voltage breakdown (RBD) testing. TDDB results from 1200V Gen3 MOSFETs reveal a field acceleration parameter of about 35 nm/V, similar to values reported for SiO2 on silicon. Temperature-dependent RBD tests of large capacitors from 25°C to 200°C reveal an apparent activation energy of 0.24eV, indicating that oxide lifetime increases as the temperature is decreased, as expected. Using this acceleration parameter and activation energy in the linear field model, the gate oxide lifetime from MOSFET TDDB testing extrapolates to greater than 108 hours at a gate voltage of 15 VGS at 175°C.

Industrial and Body Diode Qualification of Gen-III Medium Voltage SiC MOSFETs: Challenges and Solutions

In this work, we report the results of industrial qualification tests run on medium voltage SiC MOSFETs rated for 3.3 kV/40 A and 10 kV/15 A. The JEDEC JESD47J.01 standard was used as a guideline to conduct HTRB (High Temperature, Reverse Bias), HTGB (High Temperature, Gate Bias), and TDDB (Time Dependent Dielectric Breakdown) tests. No devices were found to have failed the qualification tests, and long oxide lifetime was projected for constant operation under positive bias. This paper also reports for the first time the results of qualification testing of the MOSFET body diode on a large population of medium voltage SiC MOSFETs. Constant current stress at a current equal to the device forward rating was applied for 1000 hours. No degradation of any device parameter was observed for 3 lots of devices at both the 3.3 kV and 10 kV voltage rating.

Optical and electrical characterization methods of plasma-induced damage in silicon nitride films

We proposed evaluation methods of plasma-induced damage (PID) in silicon nitride (SiN) films. The formation of an oxide layer by air exposure was identified for damaged SiN films by X-ray photoelectron spectroscopy (XPS). Bruggeman’s effective medium approximation was employed for an optical model consisting of damaged and undamaged layers, which is applicable to an in-line monitoring by spectroscopic ellipsometry (SE). The optical thickness of the damaged layer — an oxidized layer — extended after plasma exposure, which was consistent with the results obtained by a diluted hydrofluoric acid (DHF) wet etching. The change in the conduction band edge of the damaged SiN films was presumed from two electrical techniques, i.e., current–voltage (I–V) measurement and time-dependent dielectric breakdown (TDDB) test with a constant voltage stress. The proposed techniques can be used for assigning the plasma-induced structural change in an SiN film widely used as an etch-protecting layer.

Effect of surface roughness of trench sidewalls on electrical properties in 4H-SiC trench MOSFETs

The effects of the surface roughness of trench sidewalls on electrical properties have been investigated in 4H-SiC trench MOSFETs. The surface roughness of trench sidewalls was well controlled and evaluated by atomic force microscopy. The effective channel mobility at each measurement temperature was analyzed on the basis of the mobility model including optical phonon scattering. The results revealed that surface roughness scattering had a small contribution to channel mobility, and at the arithmetic average roughness in the range of 0.4–1.4 nm, there was no correlation between the experimental surface roughness and the surface roughness scattering mobility. On the other hand, the characteristics of the gate leakage current and constant current stress time-dependent dielectric breakdown tests demonstrated that surface morphology had great impact on the long-term reliability of gate oxides.

Time-dependent dielectric breakdown characterizations of interlayer dielectric damage induced during plasma processing

We proposed an electrical evaluation method on the basis of leakage current–stress time (I–t) measurement for plasma-induced damage (PID) in interlayer dielectric films. The I–t measurement, which is widely used for the time-dependent dielectric breakdown (TDDB) test is applied to the evaluation of PID in thick SiO2 films. We focus on the electron trapping process during the TDDB test. The initial stage of time evolution of leakage current is monitored, and compared among the samples damaged under various plasma conditions. It was found that the initial electron trapping rate depends on the amount of damage, i.e., the rate increases with increasing in process time (tpr) and dc self-bias voltage (Vdc). The proposed technique can be used to assess the reliability degradation of interlayer dielectric films caused by PID.

Polarity dependent thermochemical E-model for describing time dependent dielectric breakdown in metal-oxide-semiconductor devices with hyper-thin gate dielectrics

The Lorentz factor L, which is used for describing the local electric fields in hyper-thin (<3.0 nm) gate dielectrics, is found to be polarity dependent for an inversion and accumulation-mode testing of Metal-Oxide-Semiconductor Field Effect Transistors. L is strongly impacted by the dipole layers that are induced in the depletion regions in the poly and silicon-substrate electrodes. While time dependent dielectric breakdown (TDDB) results are much improved with the inversion-mode testing, the reason for this is due to a smaller Lorentz factor (thus smaller Eloc). In fact, when compared at the same local electric field Eloc, there is no difference in TDDB between the inversion and accumulation mode testing. Thus, when properly corrected for the depletion effects in the MOS electrodes, the Thermochemical E-Model becomes polarity dependent and describes well both the inversion and accumulation-mode TDDB testing of the hyper-thin gate dielectrics.

Failure Analysis of a SiC MOS Capacitor with a Poly-Si Gate Electrode

The failure mechanism of a SiC metal-oxide-semiconductor capacitor with a poly-Si gate electrode was investigated by time-dependent dielectric breakdown testing under a 200-nA constant current stress. The capacitor exhibited both hard and soft breakdowns. After dielectric breakdown in both cases, adjacent concaves were observed on the capacitor with a field-emission scanning electron microscope. Additional optical beam-induced resistance changes and photo-emission analysis of a capacitor after hard-breakdown located a failure point on the periphery of a group of adjacent concaves. Cross-sectional scanning transmission electron microscope observation revealed that a narrow, vertical defect had formed at this point on the SiC substrate.