Thru-silicon Vias Research Articles

Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis

Three-dimensional (3D) integration is a key technology for systems whose performance and power requirements cannot be achieved by traditional silicon technologies. 3D chips consist of two or more stacked silicon dies connected by short inter-die wires called Thru-Silicon-Vias (TSVs). Despite its potential, the poor reliability and yield, thermal management and testing issues remain major challenges of 3D integration. We address the TSV interconnect test challenge of 3D chips by using Interconnect Built-In Self-Test (IBIST) techniques. The proposed test strategy must sensitize structural faults like opens and shorts, and delay faults due to crosstalk. A possible approach is the well-known Maximum Aggressor Fault (MAF) model. Unfortunately, this model is too conservative and it leads to long test sequences and non-negligible hardware costs. Therefore, we present an alternative solution: the Kth-Aggressor Fault (KAF) model. In our model, aggressors of victim wires are neighboring wires within an optimized distance order K. The aggressor order K is technology-dependent and is determined such that the test times are minimal and the fault coverage is maximal. KAF-based IBIST implementation targeting TSV tests occupies three times less area than similar MAF-/marching-based implementations. We also propose a reconfigurable KAF-based IBIST implementation where tests can be performed using different aggressor orders K. Although the reconfigurable IBIST area is significant, interconnect tests during system lifetime can be performed using lower aggressor orders, reducing test duration and improving TSV availability.

A Novel Compact Thru-silicon-via On-chip Passive MMW Bandpass Filter for 77GHz Applications

This paper presents a novel on-chip passive bandpass fllter for millimeter-wave (MMW) applications that utilizes a pair of electrically-coupled thru-silicon vias (TSV). The presented TSV bandpass fllter can be used in MMW applications such as radar, medical imaging, and communication. The TSV bandpass fllter uses two TSVs to extend two electrically-coupled conductors into the silicon substrate in the z-direction instead of horizontally in the x-y plane. There is a metal layer on the bottom side of the silicon substrate that shorts the ends of the two TSVs to ground. Using TSVs in the bandpass fllter design reduces the silicon area required to implement the fllter compared to the silicon area required for the equivalent conventional fllter in the above-silicon metal-dielectric interconnect stack. The operating performance of the bandpass fllter is controlled at the design stage by choosing the separation distance between the TSVs. In this work, the two TSVs were 145m in height (z-direction) and 3m £ 50m in the x-y plane. The long edges of the TSVs (50m long edges) faced each other to maximize capacitance coupling between the TSV pair. The TSVs were separated by a distance of 5m. Full-wave electromagnetic simulations of a TSV fllter designed in an IBM SiGe technology that included TSVs show a minimum pass-band insertion loss of i3:9dB at 77GHz with a usable pass band from 75{85GHz is possible. The simulated operating range of the TSV bandpass fllter design presented in this paper show that it is well suited for automotive radar applications.