Throughput Overhead Research Articles

Scalable Blockchain Technology for Tracking the Provenance of the Agri-Food

Due to an increase in agricultural mislabeling and carelesshandling of non-perishable foods in recent years, consumers have been calling for the food sector to be more transparent. Due to information dispersion between divisions and the propensity to record inaccurate data, current traceability solutions typically fail to provide reliable farm-to-fork histories ofproducts. The three most enticing characteristics of blockchain technology areopenness, integrity, and traceability, which make it a potentially crucial tool for guaranteeing the integrity and correctness of data. In this paper, we suggest a permissioned blockchain system run by organizations, such as regulatory bodies, to promote the origin-tracking of shelf-stable agricultural products. We propose a four-tiered architecture, parallel side chains, Zero-Knowledge Proofs (ZKPs), and Interplanetary File Systems (IPFS). These ensure that information about where an item came from is shared, those commercial competitors cannot get to it, those big storage problems are handled, and the system can be scaled to handle many transactions at once. Thesolution maintains the confidentiality of all transaction flows whenprovenance data is queried utilizing smart contracts and a consumer-grade reliance rate. Extensive simulation testing using Ethereum Rinkeby and Polygon demonstrates reduced execution time, latency, and throughput overheads.

Genuinely distributed Byzantine machine learning

Machine learning (ML) solutions are nowadays distributed, according to the so-called server/worker architecture. One server holds the model parameters while several workers train the model. Clearly, such architecture is prone to various types of component failures, which can be all encompassed within the spectrum of a Byzantine behavior. Several approaches have been proposed recently to tolerate Byzantine workers. Yet all require trusting a central parameter server. We initiate in this paper the study of the “general” Byzantine-resilient distributed machine learning problem where no individual component is trusted. In particular, we distribute the parameter server computation on several nodes. We show that this problem can be solved in an asynchronous system, despite the presence of frac{1}{3} Byzantine parameter servers (i.e., n_{ps} > 3f_{ps}+1) and frac{1}{3} Byzantine workers (i.e., n_w > 3f_w), which is asymptotically optimal. We present a new algorithm, ByzSGD, which solves the general Byzantine-resilient distributed machine learning problem by relying on three major schemes. The first, scatter/gather, is a communication scheme whose goal is to bound the maximum drift among models on correct servers. The second, distributed median contraction (DMC), leverages the geometric properties of the median in high dimensional spaces to bring parameters within the correct servers back close to each other, ensuring safe and lively learning. The third, Minimum-diameter averaging (MDA), is a statistically-robust gradient aggregation rule whose goal is to tolerate Byzantine workers. MDA requires a loose bound on the variance of non-Byzantine gradient estimates, compared to existing alternatives [e.g., Krum (Blanchard et al., in: Neural information processing systems, pp 118-128, 2017)]. Interestingly, ByzSGD ensures Byzantine resilience without adding communication rounds (on a normal path), compared to vanilla non-Byzantine alternatives. ByzSGD requires, however, a larger number of messages which, we show, can be reduced if we assume synchrony. We implemented ByzSGD on top of both TensorFlow and PyTorch, and we report on our evaluation results. In particular, we show that ByzSGD guarantees convergence with around 32% overhead compared to vanilla SGD. Furthermore, we show that ByzSGD’s throughput overhead is 24–176% in the synchronous case and 28–220% in the asynchronous case.

S2p: Provenance Research for Stream Processing System

The main purpose of our provenance research for DSP (distributed stream processing) systems is to analyze abnormal results. Provenance for these systems is not nontrivial because of the ephemerality of stream data and instant data processing mode in modern DSP systems. Challenges include but are not limited to an optimization solution for avoiding excessive runtime overhead, reducing provenance-related data storage, and providing it in an easy-to-use fashion. Without any prior knowledge about which kinds of data may finally lead to the abnormal, we have to track all transformations in detail, which potentially causes hard system burden. This paper proposes s2p (Stream Process Provenance), which mainly consists of online provenance and offline provenance, to provide fine- and coarse-grained provenance in different precision. We base our design of s2p on the fact that, for a mature online DSP system, the abnormal results are rare, and the results that require a detailed analysis are even rarer. We also consider state transition in our provenance explanation. We implement s2p on Apache Flink named as s2p-flink and conduct three experiments to evaluate its scalability, efficiency, and overhead from end-to-end cost, throughput, and space overhead. Our evaluation shows that s2p-flink incurs a 13% to 32% cost overhead, 11% to 24% decline in throughput, and few additional space costs in the online provenance phase. Experiments also demonstrates the s2p-flink can scale well. A case study is presented to demonstrate the feasibility of the whole s2p solution.

A Thread Level SLO-Aware I/O Framework for Embedded Virtualization

With the development of virtualization technology, it is practical and necessary to integrate virtual machine software into embedded systems. I/O scheduling is important for embedded systems, because embedded systems always face different situations and their requests have more diversity on the requirement of real-time and importance. However, the semantic information associated with the I/O data is completely lost when crossing the virtualized I/O software stack. Here, we present an I/O scheduling framework to connect the semantic gap between the application threads in virtual machines and hardware schedulers in the host machine. Therefore, the details for the I/O request can be passed through the layers of the software stack and each layer can get the specific information about the device environment. Also, various scheduling points have been provided to implement different I/O strategies. Our framework was implemented based on Linux operating system, KVM, QEMU and virtio protocol. A prototype scheduler, Orthrus , was implemented to evaluate the effectiveness of the framework. Comprehensive experiments were conducted and the results show that our framework can guarantee the real-time requirements, and reserve more system resources for critical tasks, with negligible memory consumption and throughput overhead.

Reliable advanced encryption standard hardware implementation: 32- bit and 64-bit data-paths

Cryptographic primitives are extensively used in today's applications to provide the desired security. Malicious or accidental faults that occur in the hardware implementations of cryptographic primitives, specifically in this paper the Advanced Encryption Standard (AES), can result in an erroneous output of encryption/decryption process and reduce the reliability of the cryptographic hardware. The use of a suitable fault-tolerant scheme for AES, to recover it from failures or attacks and bring it back to an operational state, is crucial for reliability, and consequently for security purposes. In this paper, two novel online fault-tolerant schemes are proposed for AES. In the proposed fault-tolerant architecture, the round path is modified and divided it into two pipeline stages. The proposed fault-tolerant schemes are based on a combination of hardware and time redundancies, where a new hardware redundancy is proposed for the AES round function and a time redundancy for the hardware of the AES key expansion unit. The presented fault-tolerant schemes are valid for all versions of AES and are independent of its S-box implementation manner. Both ASIC and FPGA implementations of the original and the proposed fault-tolerant AES along with Full TMR (Triple Modular Redundancy) and Full TTR (Triple Time Redundancy) structures are reported as traditional fault-tolerant schemes. It is shown that the first proposed fault-tolerant architecture, named TMRrp&TTRke32, outperforms these approaches and the previous report in the literature in terms of area overhead and therefore power consumption. Also, the other approach, named TMRrp&TTRke64, is better than the other approaches in achieving a trade-off between area overhead and throughput overhead.

PIMP My Many-Core: Pipeline-Integrated Message Passing

To improve the scalability, several many-core architectures use message passing instead of shared memory accesses for communication. Unfortunately, Direct Memory Access (DMA) transfers in a shared address space are usually used to emulate message passing, which entails a lot of overhead and thwarts the advantages of message passing. Recently proposed register-level message passing alternatives use special instructions to send the contents of a single register to another core. The reduced communication overhead and architectural simplicity lead to good many-core scalability. After investigating several other approaches in terms of hardware complexity and throughput overhead, we recommend a small instruction set extension to enable register-level message passing at minimal hardware costs and describe its integration into a classical five stage RISC-V pipeline.

Fault diagnosis architecture for SKINNY family of block ciphers

Cryptographic hardware and software applications are prone to various attacks either from the environments or from the attacker to gain the secret key. Resource-constrained devices use lightweight cryptographic algorithms to achieve a high level of security. It's always a trade-off between efficient resource utilization and level of security. Out of different attacks, in recent years, fault injection attacks is well matured. It becomes imperative to choose the best and efficient fault diagnosis schemes for lightweight cryptography. In this paper, we propose novel Concurrent error detection (CED), i.e., recomputing with inverted operands (REIO) method for SKINNY Family of Block Ciphers to increase the reliability. The proposed fault detection technique for SKINNY round-based pipelined architecture is adapted. The result shows that the throughput overhead of the SKINNY remains within 2.5% variance for the proposed novel fault detection with a pipelined technique, a maximum of 10% area overhead. We have implemented the proposed fault detection scheme using Xilinx FPGA. Best to our knowledge, there is no CED based fault detection technique proposed in the literature for the SKINNY family of block ciphers. The implementation results show that the proposed scheme is more effective and well suited for resource-constrained environments.

Performance Analysis of Energy Efficient and Reliable Protocols for Intra & Inter Cluster Communications in Wireless Sensor Networks

The discovery and the use of many wireless technologies are paving way for new remote monitoring applications. The sensing devices are becoming popular because of their flexibility, performance, low cost and portability. Wireless Sensor Networks (WSN) is a good alternative to wired systems because of easy deployment in remote areas. Wireless Sensor Networks are used in different domains for various applications because of their salient characteristics like reduced power consumption, scalability, ability to respond immediately within a short span of time, reliability, dynamic in nature, low cost and easy installation. The main objective of this paper work is to find a suitable energy efficient, scalable and reliable communication protocols for intra-cluster and intercluster communication. Therefore the proposed research work follows three different phases. To achieve the desired results, the proposed research work concentrates on three protocols namely Energy Efficient and Reliable Clustering Routing Protocol (EERCRP), Energy Efficient and Reliable MAC Protocol (EERMAC) and Energy Efficient and Reliable Hybrid Transport Protocol (EERHTP).EERCRP and EERMAC are intra-cluster communication protocols that help in cluster formation and effective data sensing. EERHTP is a transport layer protocol that is used for inter-cluster communication. All the above protocols are evaluated using network simulator NS2 for their performance analysis. EERCRP is compared with PASCC and PCDCC which from the root level header node are existing congestion and queue based hybrid clustering protocols. The proposed EERCRP follows hierarchical cluster formation where the leader node is selected based on queue length, residual energy of the node and distance. It is efficient than the existing methods in terms of energy and reliability metrics.EERMAC is compared with existing MAC protocols namely SMAC, IEEE 802.11 EDCA and EA-MAC. SMAC follows traditional TDMA or CSMA method of data access. They are suitable only for periodic data sensing. The proposed EERMAC allows hybrid data sensing consisting of both periodic and event based data which are classified using priority levels. Event based data is assigned higher priority than periodic data. Queues are used for storing both types of data using various levels of threshold values. EERMAC uses CSMA/CA method for event based data. Variable TDMA method is used for event based and periodic data. EERHTP is a transport layer protocol that uses two types of reliability models namely ACK and NACK depending on the type of data. All the three protocols are evaluated both for energy and reliability metrics such as total energy consumption, residual energy comparison, energy consumption per packet, packet delivery ratio, delay, packet drop, jitter, throughput and network routing overhead. Thus it is concluded that all the three protocols are more optimal than the existing protocols and prove to be the best protocols for intracluster and inter-cluster communications.

A Single Error Correcting Code with One-Step Group Partitioned Decoding Based on Shared Majority-Vote

Technology scaling has led to an increase in density and capacity of on-chip caches. This has enabled higher throughput by enabling more low latency memory transfers. With the reduction in size of SRAMs and development of emerging technologies, e.g., STT-MRAM, for on-chip cache memories, reliability of such memories becomes a major concern. Traditional error correcting codes, e.g., Hamming codes and orthogonal Latin square codes, either suffer from high decoding latency, which leads to lower overall throughput, or high memory overhead. In this paper, a new single error correcting code based on a shared majority voting logic is presented. The proposed codes trade off decoding latency in order to improve the memory overhead posed by orthogonal Latin square codes. A latency optimization technique is also proposed which lowers the decoding latency by incurring a slight memory overhead. It is shown that the proposed codes achieve better redundancy compared to orthogonal Latin square codes. The proposed codes are also shown to achieve lower decoding latency compared to Hamming codes. Thus, the proposed codes achieve a balanced trade-off between memory overhead and decoding latency, which makes them highly suitable for on-chip cache memories which have stringent throughput and memory overhead constraints.

Mobility-Driven Association Policies for Dense Wireless Networks

The primary approach to increase coverage and capacity in infrastructure-based wireless networks is densification. Densification, however, presents a major challenge when serving mobile users, which is the overhead associated with the increased rate of base station handovers. Assuming a prior knowledge of a mobile’s trajectory and base stations’ locations, we formulate the problem of determining the sequence of handovers that optimize the trade-off between the mobile user’s perceived throughput and handover overheads in noise-limited environments. Under appropriate conditions, we show that the problem reduces to determining a maximum weight path in a directed acyclic graph induced by the mobile user’s trajectory. In practice, knowledge of a mobiles’ trajectory may be limited and one may also want to limit the handover complexity, whence we propose a new class of mobility-driven greedy association policies. The greedy policies are based on defining a handover support set, which constrains both the possible handovers and the complexity/information requirements. In a setting where base station locations follow a Poisson point process, we show that the performance of such handover processes follows a continuous-time Markov process which can be analyzed using complex variable techniques. This enables one to explore the optimization size/shape of the handover support set for mobility-driven greedy handover strategies and their relative performance compared to traditional association policies.

Evaluation of black hole attack with avoidance scheme using AODV protocol in VANET

Applying the ad hoc network on vehicles has formed a new kind of network called VANET. The higher speed of the nodes (vehicles) and frequent change in network topology make this type of network different from the traditional MANET. VANET is implemented for safety of the vehicles and to make road traffic better. Therefore, before implementing the VANET, the security of the network must be considered. We have carried out analysis of attacks and their affects that can be mounted on VANET. Hence the evaluation of attacks in VANET should be performed before implementing it. Here, in this research paper we have carried out the evaluation of the Black Hole attack (BHA) in City, Highway, and combination of both scenarios based on throughput, packet drop and routing overhead. A comparison of attack in different scenarios is also drawn which gives the clear picture of the effects of the attack in scenarios. Graphs have been drawn using MATLAB

Reliable and energy-aware routing in mobile ad-hoc networks

In a Mobile Ad-hoc Network (MANET), energy-awareness is a crucial design issue as it consists of a group of mobile nodes. The mobile nodes with limited battery power act as router in MANET. Though establishment of an appropriate and efficient route is an important design aspect, a more challenging task is to establish and select a reliable and energy-efficient route between a source-destination pair. Thus, power failure of mobile nodes constituent a route influences data routing, link failure and network lifetime. Therefore, to meet the above mentioned goal and overcome energy-aware routing design issues, in this paper routing protocols are proposed to construct reliable and energy-aware routes considering energy consumption and remaining energy of nodes. The remaining energy and energy_factor (the ratio of remaining energy and initial energy of a node) are used as important parameters for selection of a node in a route. Under considered parameters, the proposed routing protocols ensure reliability and energy-awareness in MANET and avoid link failure due to node's low power in an established route. Simulation results show that the proposed routing protocols perform better compared to the similar kind of popular existing routing schemes in terms of energy consumption, throughput, delay and routing overhead in different network scenarios.

SGX-Tor: A Secure and Practical Tor Anonymity Network With SGX Enclaves

With Tor being a popular anonymity network, many attacks have been proposed to break its anonymity or leak information of a private communication on Tor. However, guaranteeing complete privacy in the face of an adversary on Tor is especially difficult, because Tor relays are under complete control of world-wide volunteers. Currently, one can gain private information, such as circuit identifiers and hidden service identifiers, by running Tor relays and can even modify their behaviors with malicious intent. This paper presents a practical approach to effectively enhancing the security and privacy of Tor by utilizing Intel SGX, a commodity trusted execution environment. We present a design and implementation of Tor, called SGX-Tor, that prevents code modification and limits the information exposed to untrusted parties. We demonstrate that our approach is practical and effectively reduces the power of an adversary to a traditional network-level adversary. Finally, SGX-Tor incurs moderate performance overhead; the end-to-end latency and throughput overheads for HTTP connections are 3.9% and 11.9%, respectively.

Load balance technique with adaptive position updates (LAPU) for geographic routing in MANETs

In geographic routing, position updates and load distribution are crucial to achieve a good performance. There is a concern with load distribution when it comes to dense network where there are large number of connections and huge traffic. Load balanced, Adaptive Position Update (LAPU) routing protocol solves the problem of load distribution among paths in a network with reduced position updates occurring adaptively and next hop decisions based on node’s congestion status in geographic routing. In our proposed work, to achieve load balancing, a node selects two best nodes available to the destination based on node mobility and queue length and it divides the load among them, i.e., it transfers the packets in both paths. Parameters such as end-to-end delay of packet transmission, energy consumption, throughput, and routing overhead are considered to compare the performance of the proposed work.

A time stamp-based algorithm to improve security and performance of mobile ad hoc network

Mobile ad hoc network is open medium and infrastructure-less network. Mobile ad hoc network is susceptible to various security attacks such as, black hole attack, gray hole attack, bad mouthing attack, sybil attack and worm hole attack due to open medium, infrastructure-less features and lack of in-built security. In black hole attack and gray hole attack, attacker falsely sends route reply and dropped data packets received from source node. Due to these attacks, performance of mobile ad hoc network decreases. This paper proposes a time stamp-based algorithm which is an enhanced version of existing IDSNAODV algorithm. Proposed algorithm modifies existing palling process to validate identity of observer nodes using a time stamp-based approach. Based on defined set of rules and recorded activities report, source node decides the nature of target node. The performance of proposed algorithm is evaluated using the network simulator. The proposed algorithm shows improved performance for packet delivery ratio, throughput and routing overhead as compared to existing algorithm.

Lossless Compression Decoders for Bitstreams and Software Binaries Based on High-Level Synthesis

As the density of field-programmable gate arrays continues to increase, the size of configuration bitstreams grows accordingly. Compression techniques can reduce memory size and save external memory bandwidth. To accelerate the configuration process and reduce the software startup time, four open-source lossless compression decoders developed using high-level synthesis techniques are presented. Moreover, in order to balance the objectives of compression ratio, decompression throughput, and hardware resource overhead, various improvements and optimizations are proposed. Full bitstreams and software binaries have been collected as a benchmark, and 33 partial bitstreams have also been developed and integrated into the benchmark. Evaluations of the synthesizable compression decoders are demonstrated on a Xilinx ZC706 board, showing higher decompression throughput than those of the existing lossless compression decoders using our benchmark. The proposed decoders can reduce software startup time by up to 31.23% in embedded systems and 69.83% reduction of reconfiguration time for partial reconfigurable systems.

INVESTIGATION ON ENERGY BASED DATA GATHERING APPROACH FOR WSN

Wireless Sensor Networks plays a vital role in all emerging areas of Wireless Platforms like Interne of Things (IoT), WiFi, WiMAX etc. Sensor nodes are communicated with or without the presence of administrator. Data gathering is a major issue in WSN which influences the throughput, energy and data delivery. In previous research, there was not taken efforts to focus on balanced data gathering. In this research, we propose Reliable Energy Efficient Data Gathering Approach (REEDGA) to balance data gathering and overhead. To achieve this, proposed work consists of three phases. In first phase, estimation of information gathering is implemented through stable paths. Stable paths are found based on link cost. In second phase, data gathering phase is initialized to save energy in the presence of mobile sensor nodes. Overhead is kept low while keeping round trip time of gathered data. From the analytical simulation using NS2, the proposed approach achieves better performance in terms of data delivery rate, data gathering rate, throughput, delay, link availability and control overhead.

A Robust Deafness-Free MAC Protocol for Directional Antennas in Ad Hoc Networks

Directional antennas provide many benefits such as high gain and increased transmission range in wireless networks. However, the deafness problem in directional antennas can greatly decrease transmission efficiency. For example, a source node fails to communicate with the intended destination node if the destination node is beamforming in another direction. In this paper, a deafness-free medium access control (DF-MAC) protocol for directional antennas in ad hoc networks is proposed, which is based on a code division multiple access technique. In DF-MAC, two control codes are additionally used not only for handshaking but also for overcoming the deafness problem. The proposed DF-MAC successfully solves all the four types of the deafness problem in ad hoc networks with directional antennas. To the best of authors’ knowledge, this is the first MAC protocol that completely solves all the four types of the deafness problem. Furthermore, unlike other deafness-aware MAC protocols, the proposed DF-MAC supports mobility. Simulation results show that the proposed DF-MAC outperforms the existing deafness-aware MAC protocols in terms of network throughput and control overhead in both static and mobile environments. If the deafness problem occurs frequently, the effectiveness of DF-MAC is dramatically increased.

Performance evaluation of modified hybrid handover scheme in LTE fast moving rail networks

Long-Term Evolution Advanced (LTE-A) network is an emerging technology designed for supporting high data rates. This work implements a modified handover methodology to reduce the packet loss and latency in a LTE-A high-speed rail network. The network is composed of several mobile relays, user equipment (UE) and an administrator mobile relay (AR) inside the train. A modified hybrid handover scheme has been introduced to address hard handover. This scheme combines two handover procedures with the help of DeNBs (Donor evolved Node Base station) and mobile relay attaching to serving DeNB. Here the shortest path between source and destination is found by using Euclidian distance. The use of GTP (GPRS tunnelling protocol) reduces the message overhead and saves time. Performance analysis of the proposed work is made with parameters such as packet delivery ratio, throughput and routing overhead.

Network-on-Chip based MPSoC architecture for k-mean clustering algorithm

Data and image segmentation plays pivotal role in the application of machine learning. k-means, as a tool for unsupervised clustering, is a widely used algorithm for segmentation due to its inherent simplicity and efficiency. k-means partitions datasets into subsets based on their fitness value. As such k-means is a well suited algorithm for implementation on hardware platform such as Field Programmable Gate Array (FPGA) but requires high computation time. Hardware accelerators can help in reducing the computation complexity of the algorithm. In this paper, we present a simplified multicore based scalable hardware architecture for implementation of k-means. Mean and fitness modules in proposed architecture are further unfolded to further enhance the speed of k-means clustering algorithm. The unfolding factor has to be selected by keeping the area of the target device in check. In the proposed architecture, the cores are further connected through Network on Chip (NoC) interconnect network which allows for higher scalability while elevating the bottleneck of message passing. The performance of our MPSoC architecture has been evaluated with respect to Average Speedup, Average Throughput and Area consumption with and without use of NoC interconnect. Finally, we compare the use of different NoC interconnect models with respect to maximum Operating Frequency, average Throughput and Area overhead.