Threshold Voltage Of Thin-film Transistors Research Articles

Mobility and current boosting of In-Ga-Zn-O thin-film transistors with metal capping layer oxidation

This study investigates the effect of an oxidized Ta capping layer on the boosting of field-effect mobility (μ FE) of amorphous In-Ga-Zn-O (a-IGZO) Thin-film transistors (TFTs). The oxidation of Ta creates additional oxygen vacancies on the a–IGZO channel surface, leading to increased carrier density. We investigate the effect of increasing Ta coverage on threshold voltage (V th), on-state current, μ FE and gate bias stress stability of a-IGZO TFTs. A significant increase in μ FE of over 8 fold, from 16 cm2 Vs−1 to 140 cm2 Vs−1, was demonstrated with the Ta capping layer covering 90% of the channel surface. By partial leaving the a-IGZO uncovered at the contact region, a potential barrier region was created, maintaining the low off-state current and keeping the threshold voltage near 0 V, while the capped region operated as a carrier-boosted region, enhancing channel conduction. The results reported in this study present a novel methodology for realizing high-performance oxide semiconductor devices. The demonstrated approach holds promise for a wide range of next-generation device applications, offering new avenues for advancement in metal oxide semiconductor TFTs.

Low-Voltage IGZO Field-Effect Ultraviolet Photodiode

Abstract In the era of Internet of Things (IoTs), an energy-efficient ultraviolet (UV) photodetector (PD) is highly desirable considering the massive usage scenarios such as environmental sterilization, fire alarm and corona discharge monitoring. So far, common self-powered UV PDs are mainly based on metal-semiconductor hetero-structures or p–n heterojunctions, where the limited intrinsic built-in electric field restricts further enhancement of the photoresponsivity. In this work, an extremely low-voltage field-effect UV PD is proposed using a gate-drain shorted amorphous IGZO (a-IGZO) thin film transistor (TFT) architecture. A combined investigation of the experimental measurements and technology computer-aided design (TCAD) simulations suggests that the reverse current (I R) of field-effect diode (FED) is highly related with the threshold voltage (V th) of the parental TFT, implying an enhancement-mode TFT is preferable to fabricate the field-effect UV PD with low dark current. Driven by a low bias of −0.1 V, decent UV response has been realized including large UV/visible (R 300/R 550) rejection ratio (1.9 × 103), low dark current (1.15 × 10−12 A) as well as high photo-to-dark current ratio (PDCR, ∼ 103) and responsivity (1.89 A/W). This field-effect photodiode provides a new platform to construct UV PDs with well-balanced photoresponse performance at a low bias, which is attractive for designs of large-scale smart sensor networks with high energy efficiency.

Floating body effect in indium–gallium–zinc–oxide (IGZO) thin-film transistor (TFT)

In this paper, the floating body effect (FBE) in indium-gallium-zinc-oxide (IGZO) thin-film transistor (TFT) and the mechanism of device failure caused by that are reported for the first time. If the toggle AC pulses are applied to the gate and drain simultaneously for the switching operation, the drain current of IGZO TFT increases dramatically and cannot show the on/off switching characteristics. This phenomenon was not reported before, and our study reveals that the main cause is the formation of a conductive path between the source and drain: short failure. It is attributed in part to the donor creation at the drain region during the high voltage (Vhigh) condition and in part to the donor creation at the source region during the falling edge and low voltage (Vlow) conditions. Donor creation is attributed to the peroxide formation in the IGZO layer induced by the electrons under the high lateral field. Because the donor creation features positive charges, it lowers the threshold voltage of IGZO TFT. In detail, during the Vhigh condition, the donor creation is generated by accumulated electrons with a high lateral field at the drain region. On the other hand, the floating electrons remaining at the short falling edge (i.e., FBE of the IGZO TFT) are affected by the high lateral field at the source region during the Vlow condition. As a result, the donor creation is generated at the source region. Therefore, the short failure occurs because the donor creations are generated and expanded to channel from the drain and source region as the AC stress accumulates. In summary, the FBE in IGZO TFT is reported, and its effect on the electrical characteristics of IGZO TFT (i.e., the short failure) is rigorously analyzed for the first time.

Nanoscale-doped dual-channel for improved performance and reliability of Hf: IGTO / a-IGTO thin film transistor

Amorphous oxide semiconductors are widely used in the backplane thin film transistors (TFTs) of displays and are extensively researched as materials for next-generation memory devices. However, they face reliability degradation due to stress factors such as thermal, bias, and light exposure. To mitigate these issues, extensive research is focused on improvements, including doping, enhancing crystallinity, and applying pre-and post-treatments. This study investigates the significantly improved reliability and electrical properties of amorphous indium gallium tin oxide (a-IGTO) TFTs by adopting a dual-channel configuration through simultaneous co-sputtering of HfO2 and IGTO targets. The device fabrication involved co-sputtering HfO2 and IGTO at the gate oxide interface, followed by depositing an IGTO-only layer, rather than doping the entire channel material. The effect of varying Hf concentration was evaluated by applying different HfO2 sputtering powers. Optimal hafnium doping reduced the threshold voltage of the a-IGTO TFT from −0.85V to 0.15V compared to the pristine a-IGTO TFT, while enhancing the field-effect mobility (μFE). Furthermore, the Hf-doped device exhibited improved stability, with a reduced threshold voltage shift (ΔVth) under positive (+15 V) and negative(-15 V) bias stress at 3000s, decreasing from 11.5 V to 4.8 V, and 4.7 V–1.1 V, respectively. This study proposes a novel device fabrication method to enhance the reliability of amorphous oxide semiconductor, addressing their inherent stress-related issues.

Enhanced electrical performance of InGaSnO thin-film transistors by designing a dual-active-layer structure

In this study, dual-active-layer InGaSnO (IGTO) thin-film transistors (TFTs) were designed, and their electrical properties were investigated. Consequently, compared with the single-layer IGTO (pure Ar) TFTs, the dual-layer IGTO TFTs exhibited improved electrical properties, including a high field-effect mobility of 25.1 cm2 V−1 s−1, a low threshold voltage of 0.8 V, a high on/off current ratio of 1 × 108, a small subthreshold slope of 300 mV/decade, and a low off current. Additionally, the dual-layer IGTO TFTs showed superior stability for small Vth shifts of −1.9 V and 1.8 V under gate bias stress test conditions. Band structure analysis indicated that a thin front layer of IGTO (pure Ar) can provide an appropriate carrier concentration (Ne) near the IGTO (pure Ar)/IGTO (Ar/O2) interface, whereas a thick layer of IGTO (Ar/O2) can control the channel conductance and threshold voltage of IGTO TFTs. Moreover, atomic force microscopy, X-ray photoelectron spectroscopy, and Hall effect measurement results showed that the surface roughness, oxygen vacancies, Ne, and total trap density of IGTO (Ar/O2) films and TFTs were reduced by increasing the oxygen flow rate. Over all, the high performance dual-active-layer IGTO TFTs provides insights that can contribute to developing a new generation of transparent oxide thin-film electronics.

Characteristics assessment of TFT through 2D simulation under different material and structural configurations

This paper presents a performance analysis of indium-gallium-zinc-oxide (IGZO)- and pentacene-based top-gate-top-contact (TGTC) and bottom-gate-top-contact (BGTC) thin film transistors (TFTs). Extensive simulation has been performed to assess the performances in terms of threshold voltage, subthreshold slope, on-off current ratio, mobility, and figure of merit (FoM). Results indicate a trade-off between mobility and current ratio with respect to the permittivity of the dielectric layer, where tantalum oxide (Ta2O[Formula: see text] provides the optimum result in terms of FoM. The mobility of IGZO is significantly higher for both structures, whereas the current ratio for IGZO is higher than pentacene in the BGTC configuration. Comparing the structural configurations, Ta2O5-IGZO-based BGTC achieves [Formula: see text] and [Formula: see text] better mobility and current ratio, respectively, over TGTC structures. The threshold voltage of IGZO-based TFT is observed to increase with the permittivity of the dielectric in TGTC configuration but decrease in BGTC configuration. Meanwhile, the increase in oxide and active layer thicknesses causes a decrease in the threshold voltage. Moreover, both mobility and current ratio improve with a decrease in oxide or active layer thickness. Maximum mobility of 32.30[Formula: see text]cm2/Vs and a maximum current ratio of 7.54E+08 are achieved for Ta2O5-IGZO-based BGTC TFT with 10[Formula: see text][Formula: see text]m channel thickness and 5[Formula: see text][Formula: see text]m oxide thickness.

Low-voltage solution-processed Cuprous thiocyanate Thin-Film transistors with NAND logic function

Coprous thiocyanate (CuSCN)-based thin-film transistors (TFTs) by solution-processed chitosan electrolyte are fabricated on glass substrates. Such TFTs show a low operation voltage of −2.0 V due to the large specific gate capacitance of 7.65 μF/cm2 related to electric-double-layer (EDL) formation. The threshold voltage, drain current on/off ratio and field-effect mobility are estimated to be 0.28 V, 2.0 × 103 and 0.11 cm2V−1s−1, respectively. The threshold voltage of CuSCN-based TFTs shifts significantly after laser or annealing treatment. Moreover, this work implements NAND logic function on CuSCN-based TFTs for the first time. These results offer new possibilities in the development of inorganic p-type semiconductors and single-device logic applications.

Selectively Nitrogen Doped ALD-IGZO TFTs with Extremely High Mobility and Reliability.

Achieving high mobility and reliability in atomic layer deposition (ALD)-based IGZO thin-film transistors (TFTs) with an amorphous phase is vital for practical applications in relevant fields. Here, we suggest a method to effectively increase stability while maintaining high mobility by employing the selective application of nitrous oxide plasma reactant during plasma-enhanced ALD (PEALD) at 200 °C process temperature. The nitrogen-doping mechanism is highly dependent on the intrinsic carbon impurities or nature of each cation, as demonstrated by a combination of theoretical and experimental research. The Ga2O3 subgap states are especially dependent on plasma reactants. Based on these insights, we can obtain high-performance indium-rich PEALD-IGZO TFTs (threshold voltage: -0.47 V; field-effect mobility: 106.5 cm2/(V s); subthreshold swing: 113.5 mV/decade; hysteresis: 0.05 V). In addition, the device shows minimal threshold voltage shifts of +0.45 and -0.10 V under harsh positive/negative bias temperature stress environments (field stress: ±2 MV/cm; temperature stress: 95 °C) after 10000 s.

Threshold-Voltage Extraction Methods for Atomically Deposited Disordered ZnO Thin-Film Transistors.

In this paper, we present a threshold-voltage extraction method for zinc oxide (ZnO) thin-film transistors (TFTs). Bottom-gate atomic-layer-deposited ZnO TFTs exhibit typical n-type enhancement-mode transfer characteristics but a gate-voltage-dependent, unreliable threshold voltage. We posit that this obscure threshold voltage is attributed to the localized trap states of ZnO TFTs, of which the field-effect mobility can be expressed as a gate-bias-dependent power law. Hence, we derived the current-voltage relationship by dividing the drain current with the transconductance to rule out the gate-bias-dependent factors and successfully extract the reliable threshold voltage. Furthermore, we investigated the temperature-dependent characteristics of the ZnO TFTs to validate that the observed threshold voltage was genuine. Notably, the required activation energies from the low-temperature measurements displayed an abrupt decrease at the threshold voltage, which was attributed to the conduction route change from diffusion to drift. Thus, we conclude that the reliable threshold voltage of accumulation-mode ZnO TFTs can be determined using a gate-bias-dependent factor-removed current-voltage relationship with a low-temperature analysis.

Physico-Chemical Origins of Electrical Characteristics and Instabilities in Solution-Processed ZnSnO Thin-Film Transistors

We investigate the physico-chemical origins that determine the transistor characteristics and stabilities in sol-gel processed zinc tin oxide (ZTO) thin-film transistors (TFTs). ZTO solutions with Sn/(Sn+Zn) molar ratios from 0.3 to 0.6 were synthesized to demonstrate the underlying mechanism of the electrical characteristics and bias-induced instabilities. As the Sn/(Sn+Zn) ratio of ZTO is increased, the threshold voltage of the ZTO TFTs negatively shifts owing to the gradual increase in the ratio of oxygen vacancies. The ZTO TFTs with an Sn/(Sn+Zn) ratio of 0.4 exhibit highest saturation mobility of 1.56 cm2/Vs lowest subthreshold swing and hysteresis of 0.44 V/dec and 0.29 V, respectively, due to the desirable atomic states of ZTO thin film. Furthermore, these also exhibit outstanding positive bias stability due to the low trap density at the semiconductor-dielectric interface. On the other hand, the negative bias stress-induced instability gradually increases as the proportion of tin increases because the negative bias stress instability originates from the ionization of oxygen vacancies. These results will contribute to the optimization of the composition ratio in rare-metal-free oxide semiconductors for next-generation low-cost electronics.

(Invited) Short Channel Coplanar Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors on Polyimide Substrate for High Resolution Displays

High-resolution active-matrix organic light-emitting diode (AMOLED) thin-film transistor (TFT) backplane with lower power consumption is needed for augmented reality (AR) applications. The near-to-eye format of AR terminals needs facing several technical challenges, such as higher optical efficiency, wider field of view, lighter weight, and smaller size to accelerate widespread applications. For these reasons, downscaling of TFTs with amorphous-indium-gallium-zinc-oxide (a-IGZO) or LTPS is required. The channel length should be less than 1 μm and the flexible substrate is better than glass because of light weight and very thin structure. TFT technologies on polyimide (PI) substrate can support the applications for foldable and rollable displays. For flexible AMOLED, PI layer of 10 to 20 um is widely used for foldable displays. The PI layer is coated by slot coating on the top of a carrier glass with a buffer layer of carbon nanotubes (CNTs) and graphene oxide (GO) mixture coated by spray. This layer can reduce the adhesion force between PI and glass and thus mechanical detachment can be possible. The CNTs are conducting so that it can release the electrostatic discharge (ESD) damage because CNTs/GO layer exists on the bottom side of the PI substrate. The PI substrate is covered by SiO2 and ZrAlOx layers (five layers in total starting with SiO2) by plasma enhanced chemical vapor deposition and spray pyrolysis, respectively, which acts as a gas barrier. The amorphous ZrAlOx film by spray coating can be used as a high-k gate insulator and also a gas barrier. The threshold voltage of a-IGZO TFTs tends to shift toward negative gate voltage with decreasing the channel length. In this work, a ZrAlOx passivation layer is introduced for the short channel, coplanar a-IGZO TFT. A very thin ZrAlOx layer is deposited by spray pyrolysis on the top of a-IGZO TFT at the substrate temperature of 350 ℃ before interlayer deposition. The a-IGZO TFT with a very thin ZrAlOx layer exhibits the stable threshold voltage dependence with decreasing the channel length. The 0.8 μm channel length a-IGZO TFT with ZrAlOx layer by spray pyrolysis at the substrate temperature of 350 ℃ exhibits the field-effect mobility of 7.09 cm2 V-1 s-1, the threshold voltage of -0.6 V, and on/off current ratio of 3.3 × 107. The formation of Zr-O bonds on the a-IGZO surface region reduces the carrier concentration in the a-IGZO TFT offset region, between source/drain contact and the channel, and blocks the carrier diffusion into the channel. This is the first reported self-aligned coplanar a-IGZO TFT under 1 μm channel length on a flexible substrate. Figure 1

Migration of weakly bonded oxygen atoms in a-IGZO thin films and the positive shift of threshold voltage in TFTs

Amorphous indium-gallium-zinc oxide (a-IGZO) thin films are prepared by pulsed laser deposition and fabricated into thin-film transistor (TFT) devices. In-situ x-ray photoelectron spectroscopy (XPS) illustrates that weakly bonded oxygen (O) atoms exist in a-IGZO thin films deposited at high O2 pressures, but these can be eliminated by vacuum annealing. The threshold voltage (V th) of the a-IGZO TFTs is shifted under positive gate bias, and the V th shift is positively related to the deposition pressure. A temperature variation experiment in the range of 20 K–300 K demonstrates that an activation energy of 144 meV is required for the V th shift, which is close to the activation energy required for the migration of weakly bonded O atoms in a-IGZO thin films. Accordingly, the V th shift is attributed to the acceptor-like states induced by the accumulation of weakly bonded O atoms at the a-IGZO/SiO2 interface under positive gate bias. These results provide an insight into the mechanism responsible for the V th shift of the a-IGZO TFTs and help in the production of reliable designs.

Light/electric modulated approach for logic functions and artificial synapse behaviors by flexible IGZO TFTs with low power consumption

In recent years, low power electronic devices have attracted increasing interest. Here, flexible thin-film transistors (TFTs) with In–Ga–Zn–O (IGZO) as the semiconductor channel material were fabricated on polyethylene terephthalate substrates. The device exhibits good electrical properties at low operating voltage, including a high on/off ratio of ∼7.8 × 106 and high electron mobility of ∼23.1 cm2 V−1 s−1. The device also has an excellent response to visible light. With the increase of visible light intensity, the threshold voltage of IGZO TFTs decreases continuously, but the electron mobility increases gradually. Based on the unique ability of the device to respond to light, we proposed and demonstrated that a single TFT can realize different logic operations under the light/electricity mixed modulation, including ‘AND’ and ‘OR’. In addition, we also simulated some basic artificial synaptic behaviors, including excitatory postsynaptic current and paired-pulse facilitation. Thus, IGZO TFTs operating at low voltages not only have the potential to construct multifunctional optoelectronic devices, but also provide a new idea for simplifying the design of programmable logic circuits.

Enhanced current mirror circuit by dual‐gate coplanar amorphous InGaZnO TFTs

AbstractIn this brief report, we state current mirror (CM) circuit employed by coplanar amorphous indium–gallium–zinc oxide (a‐IGZO) thin‐film transistors (TFTs) with dual‐gate structure. The 2‐TFT conventional structure with different mirroring ratios and 4‐TFT cascode type are investigated. We compared the CM circuit performances made of the dual‐gate (DG) and single‐gate (SG) TFTs. At higher mirror gain, the percentage of error increases due to the issues such as TFT performance uniformity and threshold voltage shift. It is found that the DG‐based CM circuit shows excellent mirror gain even at 10× with only 2% error.

A New Pixel Circuit Compensating for Strain-Induced Luminance Reduction in Stretchable Active-Matrix Organic Light Emitting Diode Displays

A new compensation pixel circuit is proposed for a stretchable active-matrix organic light-emitting diode (AMOLED) display. The proposed pixel circuit utilizes a double-gate structure driving thin-film transistor (TFT) and a capacitive strain sensor to compensate for the change in TFT threshold voltage and luminance reduction due to display deformation. Simulation results showed that the current error rate as a result of threshold voltage variation was less than 6.5%, even under a 15% strain. Also, the current error due to luminance reduction was reduced significantly under the 15% strain at all gray levels.

Stretching Compensation Pixel Circuit Based on Oxide Thin Film Transistor

Thin film transistors (TFTs) are the essential elements to implement active matrix organic light-emitting diode (AMOLED) display. The TFT on the AMOLED controls the emission of the OLED. Pixel circuits are being studied to improve the display quality. Poly-crystalline silicon TFT and oxide TFT have been manufactured and integrated on glass substrates for AMOLED. Various kinds of display such as foldable, rollable, wearable and stretchable displays are being studied.In stretchable displays, the device and wires manufactured on the substrate are stretched out. The resistances of wire, parasitic capacitances are affected by stretching of the substrate. In addition, when the substrate is stretched, electrical characteristic such as threshold voltage and mobility of TFT would be able to change, which results in the luminance change of the OLED. Therefore, analysis of changes in TFT is required when the substrate is stretched, and compensation circuits are required. In this study, the compensation pixel circuit is proposed for the stretchable display.To make the circuit, IGZO was used as an active layer of the TFT and deposition by RF magnetron sputter. Insulator layer was deposited for the gate insulator using atomic layer deposition (ALD) and inter layer dielectric was formed after doping of the source-drain region in the same way after doping of the source-drain region.

High‐reliability gate driver circuit to prevent ripple voltage

AbstractIn this paper, a high‐reliability gate driver circuit is proposed to prevent multiple outputs. The proposed circuit ensures reliability of the pull‐up thin‐film transistor (TFT) by periodically discharging the Q node voltage to the low‐level voltage (VGL) in the off stage. In addition, the output node is composed of two pull‐down TFTs that are driven alternately to ensure stability against bias stress. Thus, because the reliabilities of the pull‐up and pull‐down TFTs can be guaranteed simultaneously, the stability of the entire circuit is improved. Based on the simulation results, the rising and falling times of the output pulse are stable within 1.77 and 1.28 μs, respectively, even when the threshold voltage of the entire TFT is shifted by +10.0 V. In addition, the ripple voltage of the proposed circuit is almost eliminated and is within 0.79% of the total swing voltage. Moreover, through current is prevented in the proposed circuit because the turn‐on durations of the pull‐up and pull‐down units are completely nonoverlapping, which suggests that unnecessary power consumption can be eliminated. Therefore, based on 2,160 stages, the total power consumption of the proposed circuit is reduced by 34.7 mW from 276.3 to 241.6 mW.

Ultrabroadband density of states of amorphous In-Ga-Zn-O

The sub-gap density of states of amorphous indium gallium zinc oxide ($a$-IGZO) is obtained using the ultrabroadband photoconduction (UBPC) response of thin-film transistors (TFTs). Density functional theory simulations classify the origin of the measured sub-gap density of states peaks as a series of donor-like oxygen vacancy states and acceptor-like Zn vacancy states. Donor peaks are found both near the conduction band and deep in the sub-gap, with peak densities of $10^{17}-10^{18}$ cm$^{-3}$eV$^{-1}$. Two deep acceptor-like metal vacancy peaks with peak densities in the range of $10^{18}$ cm$^{-3}$eV$^{-1}$ and lie adjacent to the valance band Urbach tail region at 2.0 to 2.5 eV below the conduction band edge. By applying detailed charge balance, we show increasing the density of metal vacancy deep-acceptors strongly shifts the $a$-IGZO TFT threshold voltage to more positive values. Photoionization (h$\nu$ > 2.0 eV) of metal vacancy acceptors is one cause of transfer curve hysteresis in $a$-IGZO TFTs owing to longer recombination lifetimes as they get captured into acceptor-like vacancies.

High-Gain Transparent Inverters Based on Deuterated ZnO TFTs Fabricated by Atomic Layer Deposition

Three types of highly transparent inverter circuits, enhancement/depletion, pseudo-CMOS and feedback structures, are fabricated by using zinc-oxide thin film transistors (TFTs) with deuterium plasma immersion to adjust the threshold voltage of the depletion-mode TFTs. Their DC and AC performance are investigated and compared systematically. Especially, the feedback structure inverters demonstrate a maximum gain of −310V/V at ${V}_{DD} =10$ V, which is the highest DC gain ever to be reported for oxide TFTs. Furthermore, the frequency responses of these three inverter types are examined, showing a maximum AC gain of 210 V/V at a 10 mV amplitude input in the pseudo-CMOS inverters. These high-gain transparent inverters have great potential to be used as the common-source amplifiers in the measurement of photo-stimulated electroencephalogram signals.

Lanthanum Doping in Zinc Oxide for Highly Reliable Thin-Film Transistors on Flexible Substrates by Spray Pyrolysis.

Solution-processed metal-oxide thin-film transistors (TFTs) are considered as one of the most favorable devices for next-generation, large-area flexible electronics. In this paper, we demonstrate the excellent material properties of lanthanum-zinc oxide (LaZnO) thin films deposited by spray pyrolysis and their application to TFTs. The threshold voltage of the LaZnO TFTs shifts toward positive gate voltage, and the mobility decreases with increasing lanthanum ratio in ZnO from 0 to 20%. The purification of the LaZnO precursor (P-LaZnO) further improves the device performance. The P-LaZnO TFT exhibits a field-effect mobility of 22.43 cm2 V-1 s-1, zero hysteresis voltage, and negligible threshold voltage VTH shift under positive bias temperature stress. The enhancement in the electrical properties is due to a decrease in grain size, smooth surface roughness, and reduction in the trap density in the LaZnO film. X-ray photoelectron spectroscopy (XPS) results confirm the presence of La in the TFT channel and at/near the interface of the LaZnO and ZrOx gate insulator, leading to fewer interfacial traps. The flexible P-LaZnO TFT fabricated on the polyimide substrate exhibits a mobility of 17.64 cm2 V-1 s-1 and a negligible VTH shift under bias stress. Also, the inverter made of LZO TFTs is working well with a voltage gain of 17.74 (V/V) at 4 V. Therefore, the LaZnO TFT is a promising device for next-generation flexible displays.