Threshold Voltage Extractor Circuit Research Articles

Hardware trojans in 3-D ICs due to NBTI effects and countermeasure

Going vertical as in 3-D IC design, reduces the distance between vertical active silicon dies, allowing more dies to be placed closer to each other. However, putting 2-D IC into three-dimensional structure leads to thermal accumulation due to closer proximity of active silicon layers. Also the top die experiences a longer heat dissipation path. All these contribute to higher and non-uniform temperature variations in 3-D IC; higher temperature exacerbates negative bias temperature instability (NBTI). NBTI degrades CMOS transistor parameters such as delay, drain current and threshold voltage. While the impact of transistor aging is well understood from the device point of view, very little is known about its impact on security. We demonstrated that a hardware intruder could leverage this phenomenon to trigger the payload, without requiring a separate triggering circuit. In this paper we provide a detailed analysis on how tiers of 3-D ICs can be subject to exacerbated NBTI. We proposed to embed threshold voltage extractor circuit in conjunction with a novel NBTI-mitigation scheme as a countermeasure against such anticipated Trojans. We validated through post-layout and Monty Carlo simulations using 45nm technology that our proposed solution against NBTI effects can compensate the NBTI-effects in the 3-D ICs. With the area overhead of 7% implemented in Mod-3 counter, our proposed solution can completely tolerate NBTI-induced degraded threshold voltage shift of up to 60%.

A Resistorless CMOS Voltage Reference Based on Mutual Compensation of $V_{T}$ and $V_{\rm TH}$

A novel temperature-stable nonbandgap voltage reference without resistors is presented in this brief, which is compatible with standard digital CMOS technology. Two linear-temperature terms, i.e., thermal voltage VT and threshold voltage VTH, are utilized to realize a low-temperature-dependent voltage reference with a significant reduction of nonlinear temperature terms. A self-biased threshold-voltage extractor circuit without any resistor is used to obtain the VTH and bias currents of the whole circuit. Based on ratioed transistors biased in a strong inversion region and the inverse-function technique, a temperature-insensitive gain can be applied to the proportional-to-absolute temperature term in the reference, and a weighted sum of VT and VTH is achieved. Experimental results of the proposed voltage reference implemented with a 0.35- μm CMOS process demonstrate that the output of voltage reference is 905.5 mV, a temperature coefficient of 14.8 ppm/°C with a temperature range of 0°C-100 °C is obtained at a 3.3-V power supply, and a power-supply noise attenuation of 61 dB is achieved without any filtering capacitor while dissipating a maximum supply current of 65 μA. The active area is 100 μm ×100 μm.