Threshold Voltage Distribution Research Articles

Tuning the Intrinsic Stochasticity of Resistive Switching in VO2 Microresistors.

Vanadium dioxide (VO2) microresistors exhibit resistive switching above a certain threshold voltage, allowing them to emulate neurons in neuromorphic systems. However, such devices present intrinsic cycle-to-cycle variations in their resistances and threshold voltages, which can be detrimental or beneficial, depending on their use. Here, we study this stochasticity in VO2 microresistors with various grain sizes and dimensions, through high-resolution electrical and optical measurements across numerous cycles. Our results highlight that the cycle-to-cycle variations in threshold voltage increase as the grain size becomes comparable to the device dimensions. We also present observations of multimodal threshold voltage distributions in the smaller-length resistors. To understand the underlying phenomenon, we investigate the relationship between the device insulating resistance and threshold voltage distributions, showing that these modes could correspond to distinct percolation paths and filaments. Our findings provide the first experimentally verified guidelines for designing VO2 devices with minimized/maximized stochasticity, depending on the targeted application.

Characterizing and Optimizing LDPC Performance on 3D NAND Flash Memories

With the development of NAND flash memories’ bit density and stacking technologies, while storage capacity keeps increasing, the issue of reliability becomes increasingly prominent. Low-density parity check (LDPC) code, as a robust error-correcting code, is extensively employed in flash memory. However, when the RBER is prohibitively high, LDPC decoding would introduce long latency. To study how LDPC performs on the latest 3D NAND flash memory, we conduct a comprehensive analysis of LDPC decoding performance using both the theoretically derived threshold voltage distribution model obtained through modeling (Modeling-based method) and the actual voltage distribution collected from on-chip data through testing (Ideal case). Based on LDPC decoding results under various interference conditions, we summarize four findings that can help us gain a better understanding of the characteristics of LDPC decoding in 3D NAND flash memory. Following our characterization, we identify the differences in LDPC decoding performance between the Modeling-based method and the Ideal case. Due to the accuracy of initial probability information, the threshold voltage distribution derived through modeling deviates by certain degrees from the actual threshold voltage distribution. This leads to a performance gap between using the threshold voltage distribution derived from the Modeling-based method and the actual distribution. By observing the abnormal behaviors in the decoding with the Modeling-based method, we introduce an Offsetted Read Voltage ( Δ RV) method, for optimizing LDPC decoding performance by offsetting the reading voltage in each layer of a flash block. The evaluation results show that our Δ RV method enhances the decoding performance of LDPC on the Modeling-based method by reducing the total number of sensing levels needed for LDPC decoding by 0.67% to 18.92% for different interference conditions on average, under the P/E cycles from 3000 to 7000.

Threshold voltage uniformity improvement by introducing charge injection tuning for low-temperature poly-Si thin film transistors with metal/oxide/nitride/oxide/silicon structure

Low-temperature poly-Si thin film transistors (TFTs) with a metal/oxide/nitride/oxide/silicon structure were fabricated to investigate the feasibility of suppressing threshold voltage variations between TFTs. By applying relatively high positive and negative gate bias voltages, threshold voltage could be tuned positively and negatively, respectively, by injecting charges into the charge trap layer. Stability of threshold voltage against positive gate bias at a level close to the actual circuit operation was not degraded compared with the case of an as-fabricated TFT. A uniform threshold voltage distribution could be achieved in a preliminary test using 16 TFTs by converging threshold voltages with a target value by tuning the threshold voltage for each TFT.

Ag-GST/HfOx-based unidirectional threshold switching selector with low leakage current and threshold voltage distribution for high-density cross-point arrays

Ag-GST/HfOx-based unidirectional threshold switching selector with low leakage current and threshold voltage distribution for high-density cross-point arrays

Reaping Both Latency and Reliability Benefits With Elaborate Sanitization Design for 3D TLC NAND Flash

With the rising security concern on modern storage systems, the concept of data sanitization has been widely investigated recently. Among the existing works targeting data sanitization, an overwriting-based approach, namely one-shot sanitization, is one of the most efficient sanitization approaches. Nonetheless, we find that the one-shot sanitization approach would fail to achieve precise data sanitization for 3D TLC NAND flash, because of incurring undesired data errors. That is, how to simultaneously realize precise sanitization and high security with decent latency and reliability on emerging storage devices remains unsolved. This work proposes an elaborate sanitization design that skillfully manipulates the threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$V_{t}$</tex-math></inline-formula> ) distribution of sanitized pages. Not only does the proposed design achieve precise sanitization and high security, but it also enhances read performance and data reliability. Specifically, this work elaborately sanitizes data by merging specific <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$V_{t}$</tex-math></inline-formula> distributions of the target physical page on 3D TLC NAND flash. Besides, the proposed approach further takes lateral charge migration into consideration to improve data reliability. We conduct a series of experiments to evaluate our proposed approach on real 3D TLC NAND flash. The experiment results demonstrate the proposed approach can achieve elaborate data sanitization under various scenarios and improve read performance by 29%.

Effect of Noncircular Channel on Distribution of Threshold Voltage in 3D NAND Flash Memory.

The instability in threshold voltage (VTH) and charge distributions in noncircular cells of three-dimensional (3D) NAND flash memory are investigated. Using TCAD simulation, we aim to identify the main factors influencing the VTH of noncircular cells. The key focus is on the nonuniform trapped electron density in the charge trapping layer (CTL) caused by the change in electric field between the circular region and the spike region. There are less-trapped electron (LT) regions within the CTL of programmed noncircular cells, which significantly enhances current flow. Remarkably, more than 50% of the total current flows through these LT regions when the spike size reaches 15 nm. We also performed a comprehensive analysis of the relationship between charge distribution and VTH in two-spike cells with different heights (HSpike) and angles between spikes (θ). The results of this study demonstrate the potential to improve the reliability of next-generation 3D NAND flash memory.

Investigation of Program Efficiency Overshoot in 3D Vertical Channel NAND Flash with Randomly Distributed Traps.

The incremental step pulse programming slope (ISPP) with random variation was investigated by measuring numerous three-dimensional (3D) NAND flash memory cells with a vertical nanowire channel. We stored multiple bits in a cell with the ISPP scheme and read each cell pulse by pulse. The excessive tunneling from the channel to the storage layer determines the program efficiency overshoot. Then, a broadening of the threshold voltage distribution was observed due to the abnormal program cells. To analyze the randomly varying abnormal program behavior itself, we distinguished between the read variation and over-programming in measurements. Using a 3D Monte-Carlo simulation, which is a probabilistic approach to solve randomness, we clarified the physical origins of over-programming that strongly influence the abnormal program cells in program step voltage, and randomly distributed the trap site in the nitride of a nanoscale 3D NAND string. These causes have concurrent effects, but we divided and analyzed them quantitatively. Our results reveal the origins of the variation and the overshoot in the ISPP, widening the threshold voltage distribution with traps randomly located at the nanoscale. The findings can enhance understanding of random over-programming and help mitigate the most problematic programming obstacles for multiple-bit techniques.

Bit upset and performance degradation of NAND flash memory induced by total ionizing dose effects

In order to develop the shift model of threshold voltage distribution of the memory array in a radiation environment based on the bit upset test results of NAND Flash and study the coupling effect caused by the simultaneous performance degradation of NAND Flash fundamental modules, the experimental research on the total dose effect of two types of SLC NAND Flash memories, with a feature size of 25 nm and storage capacities of 8 and 32 Gb, respectively, was carried out. When irradiated, the partial memory array and peripheral circuit were shielded. An analytical shift model of threshold voltage distribution was developed. The model parameters are extracted from the experimental data of the 32 Gb devices, and the model and the data were in good agreement. The normalized threshold voltage distributions of the memory array at different total doses were obtained through this model, which showed the changing process of the threshold voltage distribution of the memory array more intuitively and quantitatively. The experimental results also show that the reduced voltage applied to the word line of the memory array generated by the charge pump is the cause of the performance degradation of NAND Flash. The factors that reduce the output voltage of the charge pump are the leakage current of the charge pump itself, the global leakage, the local leakage, and their coupling. Reducing the leakage of NAND Flash peripheral circuits, improving the driver of the charge pumps, and designing a data refresh strategy according to the estimation of the bit upset ratio will help improve the data retention capability in the radiation environment.

Performance Analysis of Concatenated Coding to Increase the Endurance of Multilevel NAND Flash Memory

The increasing storage density of modern NAND flash memory chips, achieved both due to scaling down the cell size, and due to the increasing number of used cell states, leads to a decrease in data storage reliability, namely, error probability, endurance (number of P/E cycling) and retention time. Error correction codes are often used to improve the reliability of data storage in multilevel flash memory. The effectiveness of using error correction codes is largely determined by the model accuracy that exhibits the basic processes associated with writing and reading data. The paper describes the main sources of disturbances for a flash cell that affect the threshold voltage of the cell in NAND flash memory, and represents an explicit form of the threshold voltage distribution. As an approximation of the obtained threshold voltage distribution, a Normal-Laplace mixture model was shown to be a good fit in multilevel flash memories for a large number of rewriting cycles. For this model, a performance analysis of the concatenated coding scheme with an outer Reed-Solomon code and an inner multilevel code consisting of binary component codes is carried out. The performed analysis makes it possible to obtain tradeoffs between the error probability, storage density, and the number of P/E cycling. The resulting tradeoffs show that the considered concatenated coding schemes allow, due to a very slight decrease in the storage density, to increase the number of P/E cycling up to 2–2.5 times than their nominal endurance specification while maintaining the required value of the bit error probability.

Triple-Threshold Path-Based Static Power-Optimization Methodology (TPSPOM) for Designing SOC Applications Using 28 nm MTCMOS Technology

The threshold voltage distribution technique is an effective way to reduce the static power consumption of integrated circuits. Several gate-level-based distribution algorithms have been proposed, but the optimization effect and run time still need further optimization when applied to very large-scale integration (VLSI) designs. This paper presents a triple-threshold path-based static power optimization methodology (TPSPOM) for low-power system-on-chip. This method obtains the path weights and cell weights from paths’ timing constraints and cells’ delay-to-power ratios, then uses them as indexes to distribute each cell to low-threshold voltage (LVT), standard-threshold voltage (SVT), or high-threshold voltage (HVT). The experimental results based on a 28 nm circuit containing 385,781 cells show that the TPSPOM method reduces static power consumption by 15.16% more than the critical-path aware power consumption optimization methodology (CAPCOM). At the same time, run time is reduced by 96.85%.

Exploiting Metadata to Estimate Read Reference Voltage for 3-D nand Flash Memory

In consumer electronics, 3-D NAND flash memory has become the state-of-the-art storage medium due to the multi-bit storage per cell and 3-D stacking technology. However, flash memory cells are commonly vulnerable to numerous types of circuit-level noise, resulting in threshold voltage distribution distortion and decreased reliability. Characterization of the threshold voltage distribution and modeling of optimal read reference voltages can help to mitigate the reliability deterioration. We provide a solution for improving the reliability of flash memories while reducing their implementation cost in this paper. The proposed pre-processing method is shown to yield a smaller number of scanning voltage steps reducing the time overhead and energy consumption of multiple read operations during the characterization of threshold voltage distributions. We propose a single state asynchronous estimation (SSAE) method to estimate optimal read reference voltages. Compared with the advanced two-state asynchronous estimation (TSAE) method, it is shown to reduce the computational and space overhead by half. Furthermore, compared with using the default read reference voltages, it is also shown to reduce RBER without exact knowledge of noise.

Improved ISPP scheme for narrow threshold voltage distribution in 3-D NAND flash memory

Three-dimensional NAND flash technology exhibits a trend of increasing bit density. The narrow threshold voltage (Vth) distribution of each program state in a chip is important for increasing the number of bits in a multilevel cell (MLC) technique. An abnormal program cell (APC), which is an excessively programmed cell whose Vth overlaps with the next program state, increases the Vth distribution width (Wv). The wide Vth distribution makes it difficult to distinguish the data stored in each cell and causes data errors. In this study, an improved incremental step pulse programming (ISPP) method to narrow the Vth distribution has been proposed. As the programming step voltage (Vstep) decreases immediately before the target cells pass the nth program verify level (PVn), the difference between Vth and PVn decreases, causing a reduction in the number of APCs. Therefore, in the improved ISPP, the Vstep is selectively reduced at the target ISPP steps at which most cells are predicted to be programmed in the next ISPP step for each program state. As a result, the Wv of the improved scheme decreases compared to the conventional scheme with the minimum increase in the total number of program pulses. Larger bit density is feasible by applying improved ISPP, resulting in high-capacity NAND flash memory.

Highly Reliable Electrochemical Metallization Threshold Switch Through Conductive Filament Engineering Using Two‐Dimensional PtSe2 Insertion Layer

AbstractElectrochemical metallization threshold switch (ECM TS) has received significant attention for various applications owing to its high ON/OFF ratio, fast switching characteristics, and simple active electrode/dielectric layer/inert electrode structures. However, the excess diffusion of active metal ions causes severe variation in threshold voltage and poor endurance. Furthermore, the small room for inert electrode metal is a problem to be solved for various applications of ECM TS. Here, a novel structure is proposed in which a two‐dimensional platinum diselenide (PtSe2) is inserted between the dielectric layer and inert electrode to engineer the conductive filament by controlling the active metal ion concentration. The low work function, superior inertness, layered structure, and smooth surface of PtSe2 insertion layer lead to thin and weak conductive filament with few active metal atoms and allow the use of various metals as inert electrode. Consequently, PtSe2‐inserted ECM TS shows high reliability in both threshold voltage distribution (σ/µ = ≈6.58%) and endurance (&gt;106 cycles). Furthermore, PtSe2‐inserted ECM TS‐based 2 × 2 cross‐bar array is proposed as AND and OR logic circuits. This study is expected to pave the way for the development of ECM TS for next‐generation electronic applications.

Activation Enhancement and Grain Size Improvement for Poly-Si Channel Vertical Transistor by Laser Thermal Annealing in 3D NAND Flash.

The bit density is generally increased by stacking more layers in 3D NAND Flash. Lowering dopant activation of select transistors results from complex integrated processes. To improve channel dopant activation, the test structure of vertical channel transistors was used to investigate the influence of laser thermal annealing on dopant activation. The activation of channel doping by different thermal annealing methods was compared. The laser thermal annealing enhanced the channel activation rate by at least 23% more than limited temperature rapid thermal annealing. We then comprehensively explore the laser thermal annealing energy density on the influence of Poly-Si grain size and device performance. A clear correlation between grain size mean and grain size sigma, large grain size mean and sigma with large laser thermal annealing energy density. Large laser thermal annealing energy density leads to tightening threshold voltage and subthreshold swing distribution since Poly-Si grain size regrows for better grain size distribution with local grains optimization. As an enabler for next-generation technologies, laser thermal annealing will be highly applied in 3D NAND Flash for better device performance with stacking more layers, and opening new opportunities of novel 3D architectures in the semiconductor industry.

Quantitative analysis of irregular channel shape effects on charge-trapping efficiency using massive 3D NAND data

The randomly fluctuating trap efficiency of taper-etched nanowire thin-film transistors was investigated by measuring a very large statistical ensemble of three-dimensional NAND flash memory cells. We made trapping in n-bit multi-level cells using incremental step pulse programming and observed the widening of the threshold voltage distribution caused by abnormal program cells. Further, we classified the components that broaden the threshold voltage distribution in both chip- and wafer-level measurements to analyze behaviors of the randomly fluctuating abnormal program cell. The variations in reading and programming operations are difficult to separate because they act simultaneously in the data reading and writing operations. For each pulse of the programming, the variations occur in reading for verification, in programming itself, and in reading after program completion. To analyze the inseparable variation, we used a method to extract only the intrinsic over-programming by removing variations in the read operation from the entire abnormal program cell. Using this extraction method, we could distinguish between the simultaneous read variation and over-programming. In particular, the unpredictable effect of the three-dimensional structure, such as the irregular shape and different radius due to the tapered channel hole profile from the nonideal etching process, was calculated and verified using experimental data. We quantitatively analyzed the experimental data one by one for each cell within the entire distribution, and each pulse of dozens in the programming scheme. This analysis provides quantitative information on the variations in charge-trapping efficiency and the threshold voltage distribution width by irregular-shaped tunneling layers.

Thermal stable and low current complementary resistive switch with limited Cu source in amorphous carbon

In this Letter, we report a complementary resistive switch (CRS) with good thermal stability and low ON current. The device is constructed with a bilayer structure composed of sputtered amorphous carbon (a-C) and thermal annealed Cu doped a-C (a-C:Cu). The Cu atoms in a-C:Cu can agglomerate to form nanosized active electrodes by thermal annealing. The Cu species can migrate and redistribute to form conductive filaments within the a-C and a-C:Cu layer through an electrochemical redox reaction. The depletion of Cu species in the a-C:Cu or a-C layer produces complementary resistive switching behaviors. Benefiting from the high thermal stability of a-C and a-C:Cu, the device works stable at a high temperature of up to 300 °C with an endurance of 104 switching cycle and narrow cycle-to-cycle distribution of threshold voltages. Furthermore, the effects of the Cu content in the a-C:Cu layer and the thickness ratio of a-C:Cu/a-C on the ON state current were studied. By limiting the content of Cu in the a-C:Cu layer, a low ON state current of 5 μA was obtained, which is among the lowest in the reported CRSs. Furthermore, a “stateful” material implication logic with the “0” and “1” states represented by a distinct combination of the resistance of each layer was implemented. The CRS is a potential and promising device for low power memory/computing applications and harsh electronics.

Impact of Surface Roughness and Material Properties of Inert Electrodes on the Threshold Voltages and Their Distributions of ReRAM Memory Cells

The paper explores the impact of the surface roughness (SR) and other material properties of metal electrodes on the statistical distributions of the switching threshold voltages, Vform, Vset, and Vreset, of a resistive memory (ReRAM) cell. The surface roughness of Pt, Ru, Co, and Cu in Cu/TaOx/Pt, Cu/TaOx/Ru, and Cu/TaOx/Co devices is extensively characterized and related to the switching characteristics of the devices. We find that SF has both impacts on the mean and on the standard deviation of the Vform, Vset, and partly also on the Vreset distributions. The surface roughness of free metal surfaces of Pt, Ru, and Co when annealed at 600 °C and 900 °C is found to increase significantly, but this increase is substantially suppressed when passivated by the thin switching layer of the solid electrolyte, such as TaOx or SiO2. The increase of SR of those metals with increasing temperature correlates well with their melting temperature. Overall, we find that the differences in surface roughness along with material properties such as the thermal conductivity and work function explain well the differences between the distributions of the threshold voltages of the ReRAM devices with Pt, Ru, and Co serving as the inert electrode.

Achievable-Rate-Aware Retention-Error Correction for Multi-Level-Cell NAND Flash Memory

Owing to the effect of data retention noise in multi-level-cell NAND flash memory, the initial threshold-voltage distributions and read voltages can no longer be used to accurately calculate log-likelihood ratios (LLRs) as the retention time increases, thus causing retention errors. To solve this problem, we first utilize the so-called “correction factors” to optimize the LLR accuracy by maximizing the achievable rate of a flash-memory system without introducing extra memory-sensing operations. We further prove that the optimization of the correction factors is a convex optimization problem and can be solved analytically. To obtain the optimal correction factors, we propose two retention-error correction schemes, referred to as offline maximum-achievable-rate correction (MARC) algorithm and online MARC algorithm, which enable the flash-memory controller to utilize the corrected LLRs that are stored in a look-up table and correct the inaccurate LLRs in real time, respectively. Motivated by the variation characteristics of the threshold-voltage distributions, we also propose an enhanced expectation–maximization (EM) algorithm to reestimate their corresponding parameters, and then adjust the read voltages. By combining the enhanced EM algorithm with the MARC algorithms, an enhanced EM-based correction strategy is developed to further boost the retention-error endurance of flash memory while avoiding excessive memory-sensing overhead. Theoretical analyses and simulation results illustrate the superiority of the proposed correction mehtods in terms of the robustness against retention errors.

Curing defects in plasma-enhanced atomic layer deposition of Al2O3 by six methods

In this paper, the Al2O3 film was fabricated by plasma-enhanced ALD (PEALD) using trimethylaluminium (TMA, Al(CH3)3) precursor. For curing defects such as hydroxyl (OH), Hydrogen, and Carbon inside Al2O3, six types of treatments combining rapid thermal annealing (RTA) or H2 plasma were applied. The comprehensive electrical characteristics such as C-VG, flat-band voltage (Vfb) were quantitatively analyzed by comparing interface trap density (Dit), oxide trapped charge density (Not), permittivity, and breakdown field. RTA is crucial to reduce Dit, Not by ∼78.2% and ∼86.7%, respectively, and enhance the breakdown field from 9 MV/cm to 14 MV/cm or higher by forming the interfacial layer. However, it was not adequate to prevent the severe Vfb shift and decrease of permittivity. H2 plasma pre-treatment could be a solution for these problems as well as slightly improve the breakdown property. But the widening of Vfb variation was still concerned because the amount of carbon reduced by H2 plasma treatment is not consistent. Thus, a more precise H2 plasma treatment is necessary for reliable threshold voltage distribution.

A low-power memristor based on 2H–MoTe2 nanosheets with synaptic plasticity and arithmetic functions

Bionic artificial synapses based on 2D transition metal dichalcogenides are comparable to biological synapses due to the unique properties, which are important for building brain-like computing to break the energy and data throughput limit of the von Neumann architecture. In this work, a two-terminal memristor with vertical structure was fabricated by using 2H–MoTe2 nanosheet dispersion. The fabricated memristor based on the Cu/MoTe2/Si structure not only exhibits the stable bipolar nonvolatile resistive switching behavior but also implements the centralized distribution of threshold voltage, and the SET/RESET power can be as low as 0.86 μW/93 nW. Impressively, classical synaptic functions including long-term potentiation/long-term depression, excitatory postsynaptic currents, spike-timing-dependent plasticity, and paired-pulse facilitation were mimicked, which attribute to the formation and rupturing of Cu conductive filaments. Interestingly, the simple arithmetic functions can be operated. Therefore, this work provides a new solution for the development of synaptic devices and neural computing research in the future.