Threshold Logic Circuits Research Articles

Constraint Solving for Synthesis and Verification of Threshold Logic Circuits

Threshold logic (TL) circuits gain increasing attention due to their feasible realization with emerging technologies and strong bind to neural network applications. In this work, we devise techniques for automatic synthesis and verification of TL circuits based on constraint solving. For synthesis, we formulate a fundamental operation to collapse TL functions, and derive a necessary and sufficient condition of collapsibility for linear combination of two TL functions. An approach based on solving the subset sum problem is proposed for fast circuit transformation. For verification, we propose a procedure to convert a TL function to a multiplexer (MUX) tree and to pseudo-Boolean (PB) constraints for formal Boolean and PB reasoning, respectively. Experiments on synthesis show that the collapse operation further reduces gate counts of synthesized TL circuits by an average of 18%. Experiments on verification demonstrate good scalability of the MUX-based method for equivalence checking of synthesized TL circuits, and efficiency of PB constraint conversion in cases where the conjunctive normal form (CNF) formula conversion and MUX tree conversion suffer from memory explosion.

High‐speed energy efficient process, voltage and temperature tolerant hybrid multi‐threshold 4:2 compressor design in CNFET technology

Compressors are fundamental components in multi-operand addition and multiplication hardware. The present study aims to propose several high-speed hybrid designs of 4:2 compressors which are implemented based on multi-threshold logic and transmission gate multiplexers, at low supply voltages. In order to implement these circuits, carbon nanotube field-effect transistors (CNFETs) are utilised. The division of the entire input capacitor network in the third proposed design causes the entire structure operates faster and consumes less power. All designs were simulated with Synopsys HSPICE and 32 nm CNFET technology in different conditions. Simulation results demonstrate the superiority of the third proposed design with regard to different load and frequency conditions. In addition, it becomes less sensitive to process, voltage and temperature variations compared to other similar capacitive threshold logic circuits. The results indicate the third proposed design outperforms the best reference design in terms of delay and power-delay product by 34 and 25%, respectively. Furthermore, the performance of each design was evaluated in a 8 × 8-bit binary multiplier as a uniform test bench, which confirmed the above results on isolated single 4:2 compressors.

Effective Logic Synthesis for Threshold Logic Circuit Design

This paper presents a novel and effective logic synthesis flow able to identify threshold logic functions during the technology mapping process. It provides more efficient logic covering, exploring also redundant cuts. Moreover, the proposed design flow takes into account different circuit area estimations, such as the sum of input weights and threshold values, the gate fanin and the number of threshold logic gates. As a result, the mapped circuits present a reduction up to 47% and 67% in area and logic depth, respectively, in comparison to the most recent related approaches.

A memristor-based long short term memory circuit

Long-short term memory (LSTM) is a cognitive architecture that aims to mimic the sequence temporal memory processes in human brain. The state and time-dependent based processing of events is essential to enable contextual processing in several applications such as natural language processing, speech recognition and machine translations. There are many different variants of LSTM and almost all of them are software based. The hardware implementation of LSTM remains as an open problem. In this work, we propose a hardware implementation of LSTM system using memristors. Memristor has proved to mimic behavior of a biological synapse and has promising properties such as smaller size and absence of current leakage among others, making it a suitable element for designing LSTM functions. Sigmoid and hyperbolic tangent functions hardware realization can be performed by using a CMOS-memristor threshold logic circuit. These ideas can be extended for a practical application of implementing sequence learning in real-time sensory processing data.

A capacitive multi-threshold threshold gate design to reach a high-performance PVT-tolerant 4:2 compressor by carbon nanotube FETs

This paper presents two new 4:2 compressors based on capacitive multi-threshold threshold logic (MTTG), and Carbon Nanotube Field Effect Transistors (CNFETs). The entire capacitor network is divided into two groups in one of the proposed designs. As a result, the number of voltage levels is reduced and the entire structure becomes less sensitive to Process, Voltage, and Temperature variations in comparison with other similar capacitive Threshold Logic (TL) circuits. All designs are simulated by Synopsys HSPICE and 32 nm CNFET technology in different situations and conditions. Simulation results demonstrate the superiority of the second proposed design. It operates 55.9% faster and consumes about 7.2% less power than the second best TL structure (CSTFA). It also operates 16.2% faster and consumes 13.6% less energy in comparison with a traditional design (BLG). Moreover, estimations show that the first proposed design occupies the least area among the capacitive TL circuits.

Implementation of a noise-coexistence threshold logic architecture on a GaAs-based nanowire FET network

Toward reconfigurable and noise-coexistence information processing system utilizing nanostructures, we study a threshold logic circuit and a double threshold function using a GaAs-based nanowire field-effect transistor (FET) network. A noise coexistence capability is based on a noise-assisted state transition in a threshold function in a threshold logic element. We fabricate a circuit reconfigurable between NAND and NOR functions. A hysteresis transfer characteristic with double threshold is realized in the GaAs nanowire by using a silicon nitride (SiN) as the gate insulator. We introduce a unique inverter design using the SiN-gate FET as a load to achieve the transfer characteristic with clockwise hysteresis, similar to a Schmitt trigger.

A Survey of Memristive Threshold Logic Circuits.

In this paper, we review different memristive threshold logic (MTL) circuits that are inspired from the synaptic action of the flow of neurotransmitters in the biological brain. The brainlike generalization ability and the area minimization of these threshold logic circuits aim toward crossing Moore's law boundaries at device, circuits, and systems levels. Fast switching memory, signal processing, control systems, programmable logic, image processing, reconfigurable computing, and pattern recognition are identified as some of the potential applications of MTL systems. The physical realization of nanoscale devices with memristive behavior from materials, such as TiO2, ferroelectrics, silicon, and polymers, has accelerated research effort in these application areas, inspiring the scientific community to pursue the design of high-speed, low-cost, low-power, and high-density neuromorphic architectures.

ATPG for Delay Defects in Current Mode Threshold Logic Circuits

An automatic test pattern generation approach to detect delay defects in a circuit consisting of current mode threshold logic gates is introduced. Each generated pattern should excite the maximum propagation delay at the fault site. Manufactured weights may vary, and maximum delay is ensured by applying an appropriately generated set of patterns per fault. Experimental results show the efficiency of the proposed methods.

Implementation Aspects of Logic Functions using Single Electron Threshold Logic Gates and Hybrid SET-MOS Circuits

ABSTRACTSingle electron technology is an attractive technology for future low-power VLSI/ULSI systems. Single electronics implies the possibility to control the movement and position of a single electron or a small amount of electrons. In this work, design, implementation, and analysis of logic functions are presented using single electron threshold logic gate (TLG) and hybrid SET-MOS circuits. The logic operation of the designed circuit is tested using Monte Carlo-based simulation tool SIMON for the single electron threshold logic circuit. For the hybrid SET-MOS-based implementation, the logic operation of the circuit is verified in Tanner environment. A compact analytical model with 11 island states for SET devices and BSIM4.6.1 model for MOS is used. The influence of thermal fluctuation on the stability of the threshold logic-based circuit, caused by increase in system temperature, has been thoroughly investigated. The effect of island states on the performance of the hybrid SET-MOS circuit is analysed. Finally, the performances of both the design approaches have been analysed and compared in terms of circuit elements, voltage levels, power consumption, and delay.

Resistive MOSFET brain-inspired threshold logic gates

The concept of a pseudo-resistive threshold logic circuit that uses a combination of CMOS inverter and bulk driven MOSFET pseudo-resistive divider circuit for designing a universal NOR gate is presented. Inspired from the neuronal firing mechanisms, the inverter implements the binary threshold decision, while pseudo-resistive circuit provides the summation of normalised weighted inputs. The proposed logic gate when tested using the TSMC 0.18 µm low voltage process show an overall improved performances in terms of area, delay and power in comparison with CMOS and pseudo NMOS logic.

Memristive Operational Amplifiers

The neuronal algorithms process the information coming from the natural environment in analog domain at sensory processing level and convert the signals to digital domain before performing cognitive processing. The weighting of the signals is an inherent way the neurons tell the brain on the importance of the inputs and digitisation using threshold logic the neurons way to make low level decisions from it. The analogue implementation of the weighted multiplication to input responses is essentially an amplification operation and so is the threshold logic comparator that can be implemented using amplifiers. In this sense, amplifiers are essential building in the development of threshold logic computing architectures. Specifically, operational amplifier would act as the best candidate for use with threshold logic circuits due to its useful properties of large gain, low output resistance and high input resistance. In this paper, a reconfigurable operational amplifier is proposed based on quantised conductance devices in combination with MOSFET devices. The designed amplifier is used to design a threshold logic cell that has the capability to work as different logic gates. The presented quantised conductance memristive operational amplifier show promising performance results in terms of power dissipation, on-chip area and THD values.

Resistive Threshold Logic

We report a resistance based threshold logic family useful for mimicking brain like large variable logic functions in VLSI. A universal Boolean logic cell based on an analog resistive divider and threshold logic circuit is presented. The resistive divider is implemented using memristors and provides output voltage as a summation of weighted product of input voltages. The output of resistive divider is converted into a binary value by a threshold operation implemented by CMOS inverter and/or Opamp. An universal cell structure is presented to decrease the overall implementation complexity and number of components. When the number of input variables become very high, the proposed cell offers advantages of smaller area and design simplicity in comparison with CMOS based logic circuits.

A Bit-Serial Reconfigurable VLSI Based on a Multiple-Valued X-Net Data Transfer Scheme

A multiple-valued data transfer scheme using X-net is proposed to realize a compact bit-serial reconfigurable VLSI (BS-RVLSI). In the multiple-valued data transfer scheme using X-net, two binary data can be transferred from two adjacent cells to one common adjacent cell simultaneously at each “X” intersection. One cell composed of a logic block and a switch block is connected to four adjacent cross points by four onebit switches so that the complexity of the switch block is reduced to 50% in comparison with the cell of a BS-RVLSI using an eight nearest-neighbor mesh network (8-NNM). In the logic block, threshold logic circuits are used to perform threshold operations, and then their binary dual-rail voltage outputs enter a binary logic module which can be programmed to realize an arbitrary two-variable binary function or a bit-serial adder. As a result, the configuration memory count and transistor count of the proposed multiplevalued cell are reduced to 34% and 58%, respectively, in comparison with those of an equivalent CMOS cell. Moreover, its power consumption for an arbitrary 2-variable binary function becomes 67% at 800MHz under the condition of the same delay time. key words: multiple-valued data transfer scheme, X-net, multiple-valued current-mode logic, MOS current-mode logic, fine-grain reconfigurable VLSI

Exploring the Potential of Threshold Logic for Cryptography-Related Operations

Motivated by the emerging interest in new VLSI processes and technologies, such as Resonant Tunneling Diodes (RTDs), Single-Electron Tunneling (SET), Quantum Cellular Automata (QCA), and Tunneling Phase Logic (TPL), this paper explores the application of the non-Boolean computational paradigms enabled by such new technologies. In particular, we consider Threshold Logic functions, directly implementable as primitive gates in the above-mentioned technologies, and study their application to the domain of cryptographic computing. From a theoretical perspective, we present a study on the computational power of linear threshold functions related to modular reduction and multiplication, the central operations in many cryptosystems such as RSA and Elliptic Curve Cryptography. We establish an optimal bound to the delay of a threshold logic circuit implementing Montgomery modular reduction and multiplication. In particular, we show that fixed-modulus Montgomery reduction can be implemented as a polynomial-size depth-2 threshold circuit, while Montgomery multiplication can be implemented as a depth-3 circuit. We also propose an architecture for Montgomery modular reduction and multiplication, which ensures feasible O(n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) area requirements, preserving the properties of constant latency and a low architectural critical path independent of the input size n. We compare this result with existing polynomial-size solutions based on the Boolean computational model, showing that the presented approach has intrinsically better architectural delay and latency, both O(1).

Low Power Current-Mode Threshold Logic Gate Using Nano-Technology Double-Gate MOSFETs

Abstract:This paper presents a new low voltage low power current mode threshold logic (CMTL)circuits using DGMOSFETs. The ultimate feature of the double gate transistor is usingthe top and bottom gates in the design of the logic circuits that reduces the number ofthe transistors. The total number of the transistors required to implement the CMTLcircuits and the power dissipation is almost reduced by half by using the DGMOSFET.OR, AND, MAJ logic gates are designed using DGMOSFETs and simulated usingHSPICE. The results for the proposed 45 nm DGMOSFET logic circuits with 1 Vsupply voltage show low power dissipation, smaller power delay product and lessnumber of device.

Multi-threshold threshold logic circuit design using resonant tunnelling devices

A novel and extremely compact circuit topology able to implement a generalised threshold logic function with two thresholds is presented. The circuit consists of resonant tunnelling diodes and heterostructure field effect transistors.

Threshold logic circuit design of parallel adders using resonant tunneling devices

Resonant tunneling devices and circuit architectures based on monostable-bistable transition logic elements (MOBILEs) are promising candidates for future nanoscale integration. In this paper, the design of clocked MOBILE-type threshold logic gates and their application to arithmetic circuit components is investigated. The gates are composed of monolithically integrated resonant tunneling diodes and heterostructure field-effect transistors. Experimental results are presented for a programmable NAND/NOR gate. Design related aspects such as the impact of lateral device scaling on the circuit performance and a bit-level pipelined operation using a four phase clocking scheme are discussed. The increased computational functionality of threshold logic gates is exploited in two full adder designs having a minimal logic depth of two circuit stages. Due to the self-latching behavior the adder designs are ideally suited for an application in a bit-level pipelined ripple carry adder. To improve the speed a novel pipelined carry lookahead addition scheme for this logic family is proposed.

Monte Carlo optimization of superconducting complementary output switching logic circuits

The authors have previously proposed a new superconducting voltage-state logic family called complementary output switching logic (COSL). This logic family has been designed using a Monte Carlo optimization process such that circuits have a high theoretical yield at 5-10 Gb/s clock speeds in spite of existing Josephson process variations. In the present work the Monte Carlo optimization process is described and theoretical yields are calculated for the COSL 2- and 3-bit encoder circuits. The circuit simulations use 5-10-GHz sinusoidal clocks and measured global and local process variations. The 2-bit encoder results are compared to modified variable threshold logic (MVTL) circuits and demonstrate that COSL circuits should have a significantly higher theoretical yield than MVTL at 10 Gb/s. Design rules for optimal COSL circuit layouts are also given, and experimental data are presented for 2-bit encoder circuits operating at multigigahertz clock frequencies. HSPICE is used for all Monte Carlo simulations and the Josephson junction model is given in the Appendix.

Modeling for stuck faults in cmos non-threshold logic (NTL) combinational circuits

In this paper, a transistor model is presented for CMOS Non Threshold Logic (NTL) combinational circuits. This model employs the logic transistor function (LTF) to examine the behavior of CMOS Non Threshold Logic (NTL) circuits. The LTF is a Boolean representation of the circuit output in terms of its input variables and its transistor topology. The LTF is automatically generated using the path algebra technique. The faulty behavior of the circuit can be obtained from the fault free LTF by using a systematic procedure. The model assumes the logic values 0, 1, I , M, where, I and M imply an intermediate logical value and a memory element, respectively. Both classical stuck-at faults and non classical transistor stuck faults can be analyzed by this model. Primitive D-cubes of the fault can be extracted for a specified subcircuit. To generate test for single or multiple faults, a variant of the D-algorithm may be used. Algorithms that were developed for Pseudo NMOS combinational circuits can be directly applied to generate test vectors.

On the node complexity of neural networks

New results are presented for the node complexity of threshold logic circuit implementations of n-input, m-output logic functions. When no restrictions are imposed on the network the node complexity is shown to be θ( m2 n (n− log m )) . One-hidden-layer networks are shown to have a node complexity of O(2 n + m) and θ( m2 n [ n( n + m )]) . Networks with weights restricted to the set {−1, 0, 1} are shown to have a node complexity of θ( m2 n ) , and networks for which fan-in is restricted to 2 are shown to have a node complexity of θ( m2 n ( n + log m )) .