Threshold Inverter Quantization Technique Research Articles

TIQ Flash ADC Design using a Low Power Multiplier Based Encoder

Threshold Inverter Quantization (TIQ) for applications of system-on-chip (SoC) depending on CMOS flash analog-to-digital converter (ADC). The TIQ technique which uses two cascaded CMOS inverters as a voltage comparator. However, this TIQ method must be created to meet the latest SoC trends, which force ADCs to be integrated with another electronic circuit on the chip and focus on low-power and low-voltage applications. TIQ comparator reduced the impact of variations in the process, temperature, and power supply voltage. Therefore, we obtained a higher TIQ flash ADC speed and resolution. TIQ flash ADC reduced / managed power dissipation. We obtain large power savings by managing the power dissipation in the comparator. Furthermore, the new comparator has a huge benefit in power dissipation and noise rejection comparative to the TIQ comparator [1]. The findings indicate that the TIQ flash ADC based on Modied mux attain heavy-speed transformation and has a tiny size, low-power dissipation and operation of lowvoltage compared to another flash ADCs.

A Novel CNFET Technology Based 3 Bit Flash ADC for Low-Voltage High Speed SoC Application

The continuous scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) led to the considerable impact in the analog-digital mixed signal integrated circuit design for system-on-chips (SoCs) application. SoCs trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design based on existing CMOS technology. In this paper, we have designed and analyzed a 3-bit high speed, low-voltage and low-power flash ADC at 32nm CNFET technology for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded carbon nanotube field effect transistor (CNFET) inverters as a comparator. The TIQ technique proposed has been developed for better implementation in SoC applications. The performance of the proposed ADC is studied using two different types of encoders such as ROM and Fat tree encoders. The proposed ADCs circuits are simulated using Synopsys HSPICE with standard 32nm CNFET model at 0.9 input supply voltage. The simulation results show that the proposed 3 bit TIQ technique based flash ADC with fat tree encoder operates up to 8 giga samples per second (GSPS) with 35.88µW power consumption. From the simulation results, we observed that the proposed TIQ flash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other low power CMOS technology based flash ADCs. The proposed method is sensitive to process, temperature and power supply voltage variations and their impact on the ADC performance is also investigated.

Low Power CMOS Data Converter with SNDR analysis for High Speed System On Chip Applications

In modern era of advanced VLSI design the transistor sizing and scaling has an considerable impact. There are very essential two constrains, which needs serious attention to the VLSI chip designer are high speed and low power consumption. Therefore in this paper an 8-bit 3 Gs/sec flash analog-to-digital data converter (ADC) in 45nm CMOS technology is presented for low power and high speed system-on-chip (SoC) applications. This low power 8-bit flash Analog to Digital data converter comprises 255 comparators and one thermometer to binary encoder. This flash ADC design is an extended research work of the earlier work related to ADC design using CMOS process technology. The schematic simulation of ADC is done in Tanner-Spice Pro (S-Edit) and layout simulation is done in Tanner-Spice Pro (L-Edit) V.15.14. The Simulated result shows the power consumption in Flash ADC is 41.78μw. The Threshold Inverter Quantization (TIQ) technique is proposed to get WPMOS/WNMOS < 1 for transistors to keep the power consumption as low as possible. It is also observed that the ADC consumes 41.78μW of peak power and 6.45μW of average power at full speed while it operates on a power supply voltage of 0.6V. Compared with the earlier work, this project consumes less power and high speed with proposed TIQ technique gives an edge in SoC based VLSI design. Finally the Signal to Noise Distortion analysis is done to obtain more precise data conversion results. The SNDR was found 31.9dB for ultimate precise data conversion using 45nm CMOS process technology.

Employing Threshold Inverter Quantization (TIQ) technique in designing 9-Bit folding and interpolation CMOS analog-to-digital converters (ADC)

This paper presents design and implementation of a 9-bit folding and interpolation ADC using 0.35 µm CMOS C35B4 model under AMS-HIT Kit Library. The complete system consists of two main blocks. One of them is 4-bit flash ADC, which is based on the so-called Threshold Inverter Quantization (TIQ) technique. This part forms the coarse part of the data conversion process. The second one is the 5-bit fine ADC part of the converter. This block includes comparator, analog pre-processing and interpolation units. The designed converter works with 5 V power supply, and has analog input range of 3.4 Vpp. Analog input bandwidth is 1 MHz with clock frequency of 2 GHz for the digital part. The linearity measures of the converter include 2.9 LSB of DNL and 6.3 LSB of INL. The main purpose of this work is to investigate the possibility of employing TIQ technique in designing folding and interpolation type of ADCs. Although, the linearity measures are not satisfying for 9-bit case, the authors believe that this case study will serve as a preferred reference for the researchers who are willing to use TIQ technique in designing fast ADCs other than flash scheme especially. Key words: Threshold inverter quantization, flash analog-to-digital converter, folding and interpolation analog-to-digital converter.